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coreboot-kgpe-d16/src/northbridge/amd/agesa/dimmSpd.h

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AMD Steppe Eagle: Add northbridge files for new SoC family Add the northbridge file for AMD's new Mullins and Steppe Eagle processor family. Since the processor family name is not the same across AMD's sales and marketing channels, I have elected to use part of the processor ID as the family name. The intent is to reduce confusion since the processor ID is the same for both families. This northbridge support has only been validated on the AMD Embedded variants ("Steppe Eagle"). The AGESA wrappers in coreboot have a function that is intended to mirror the UMA memory allocation performed during memory initialization by AGESA. Update the Steppe Eagle memory allocation to mimic the memory reservation done inside the AGESA BLOB. Change the default CBMEM address, the default video BIOS device ID, and a couple of other defaults to match changes in coreboot community code. The northbridge chip.h specifies how many processor sockets, how many channels, and how many DIMM slots are supported by the northbridge. Steppe Eagle does not permit multisocket systems and has only one memory controller channel. Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6678 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-15 19:46:25 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _DIMMSPD_H_
#define _DIMMSPD_H_
AGESA_STATUS
AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
AGESA fam15tn fam16kb 00730f01: Add common agesa_readSpd() Remove northbridge specific callouts for AGESA_READ_SPD. Move low-level SMBus code to southbridge. Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7112 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-17 21:33:22 +02:00
int hudson_readSpd(int spdAddress, char *buf, size_t len);
int smbus_readSpd(int spdAddress, char *buf, size_t len);
AMD Steppe Eagle: Add northbridge files for new SoC family Add the northbridge file for AMD's new Mullins and Steppe Eagle processor family. Since the processor family name is not the same across AMD's sales and marketing channels, I have elected to use part of the processor ID as the family name. The intent is to reduce confusion since the processor ID is the same for both families. This northbridge support has only been validated on the AMD Embedded variants ("Steppe Eagle"). The AGESA wrappers in coreboot have a function that is intended to mirror the UMA memory allocation performed during memory initialization by AGESA. Update the Steppe Eagle memory allocation to mimic the memory reservation done inside the AGESA BLOB. Change the default CBMEM address, the default video BIOS device ID, and a couple of other defaults to match changes in coreboot community code. The northbridge chip.h specifies how many processor sockets, how many channels, and how many DIMM slots are supported by the northbridge. Steppe Eagle does not permit multisocket systems and has only one memory controller channel. Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6678 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-15 19:46:25 +02:00
#endif
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