GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/src/lib/spd_bin.c

268 lines
6.8 KiB
C
Raw Normal View History

src/lib: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id3a0b63272ebda3dad13803700bcff36d36f4815 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-02 23:48:34 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
#include <cbfs.h>
#include <console/console.h>
soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-01 09:37:38 +02:00
#include <memory_info.h>
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
#include <spd_bin.h>
#include <string.h>
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
#include <device/dram/ddr3.h>
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
void dump_spd_info(struct spd_block *blk)
{
u8 i;
for (i = 0; i < CONFIG_DIMM_MAX; i++)
if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) {
lib/spd_bin: Print out correct SMBus SPD address in dump_spd_info With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an input), SMBus SPD addresses are accepted from the mainboard and not calculated within the spd_bin library routines. Use the addr_map values to print correct address in dump_spd_info. Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08 22:28:59 +02:00
printk(BIOS_DEBUG, "SPD @ 0x%02X\n", blk->addr_map[i]);
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
print_spd_info(blk->spd_array[i]);
}
}
soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-01 09:37:38 +02:00
const char * __weak mainboard_get_dram_part_num(void)
{
/* Default weak implementation, no need to override part number. */
return NULL;
}
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
static bool use_ddr4_params(int dram_type)
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
{
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
switch (dram_type) {
case SPD_DRAM_DDR3:
case SPD_DRAM_LPDDR3_INTEL:
return false;
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-13 10:16:20 +01:00
/* Below DDR type share the same attributes */
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
case SPD_DRAM_LPDDR3_JEDEC:
case SPD_DRAM_DDR4:
case SPD_DRAM_LPDDR4:
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-13 10:16:20 +01:00
case SPD_DRAM_LPDDR4X:
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
return true;
default:
printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
dram_type, __func__);
return true;
}
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
}
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
static const char *spd_get_module_type_string(int dram_type)
{
switch (dram_type) {
case SPD_DRAM_DDR3:
return "DDR3";
case SPD_DRAM_LPDDR3_INTEL:
case SPD_DRAM_LPDDR3_JEDEC:
return "LPDDR3";
case SPD_DRAM_DDR4:
return "DDR4";
lib/spd_bin: Extend LPDDR4 SPD information Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-06 14:18:30 +01:00
case SPD_DRAM_LPDDR4:
return "LPDDR4";
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-13 10:16:20 +01:00
case SPD_DRAM_LPDDR4X:
return "LPDDR4X";
case SPD_DRAM_DDR5:
return "DDR5";
case SPD_DRAM_LPDDR5:
return "LPDDR5";
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
}
return "UNKNOWN";
}
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
static int spd_get_banks(const uint8_t spd[], int dram_type)
{
static const int ddr3_banks[4] = { 8, 16, 32, 64 };
static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
lib/spd_bin: Cleanup spd_get_banks Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-13 10:21:59 +01:00
if (use_ddr4_params(dram_type)) {
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
if (index >= ARRAY_SIZE(ddr4_banks))
return -1;
return ddr4_banks[index];
lib/spd_bin: Cleanup spd_get_banks Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-13 10:21:59 +01:00
} else {
if (index >= ARRAY_SIZE(ddr3_banks))
return -1;
return ddr3_banks[index];
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
}
}
static int spd_get_capmb(const uint8_t spd[])
{
lib/spd_bin: Extend LPDDR4 SPD information Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-06 14:18:30 +01:00
static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64,
128, 48, 96, 12, 24, 72 };
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
int index = spd[SPD_DENSITY_BANKS] & 0xf;
if (index >= ARRAY_SIZE(spd_capmb))
return -1;
return spd_capmb[index] * 256;
}
static int spd_get_rows(const uint8_t spd[])
{
static const int spd_rows[7] = { 12, 13, 14, 15, 16, 17, 18 };
int index = (spd[SPD_ADDRESSING] >> 3) & 7;
if (index >= ARRAY_SIZE(spd_rows))
return -1;
return spd_rows[index];
}
static int spd_get_cols(const uint8_t spd[])
{
static const int spd_cols[4] = { 9, 10, 11, 12 };
int index = spd[SPD_ADDRESSING] & 7;
if (index >= ARRAY_SIZE(spd_cols))
return -1;
return spd_cols[index];
}
static int spd_get_ranks(const uint8_t spd[], int dram_type)
{
static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
: DDR3_ORGANIZATION;
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
int index = (spd[organ_offset] >> 3) & 7;
if (index >= ARRAY_SIZE(spd_ranks))
return -1;
return spd_ranks[index];
}
static int spd_get_devw(const uint8_t spd[], int dram_type)
{
static const int spd_devw[4] = { 4, 8, 16, 32 };
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
: DDR3_ORGANIZATION;
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
int index = spd[organ_offset] & 7;
if (index >= ARRAY_SIZE(spd_devw))
return -1;
return spd_devw[index];
}
static int spd_get_busw(const uint8_t spd[], int dram_type)
{
static const int spd_busw[4] = { 8, 16, 32, 64 };
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH
: DDR3_BUS_DEV_WIDTH;
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
int index = spd[busw_offset] & 7;
if (index >= ARRAY_SIZE(spd_busw))
return -1;
return spd_busw[index];
}
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, size_t *len)
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
{
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
*spd_name = mainboard_get_dram_part_num();
if (*spd_name != NULL) {
*len = strlen(*spd_name);
return;
}
switch (type) {
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
case SPD_DRAM_DDR3:
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
*spd_name = (const char *) &spd[DDR3_SPD_PART_OFF];
*len = DDR3_SPD_PART_LEN;
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
break;
case SPD_DRAM_LPDDR3_INTEL:
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
*spd_name = (const char *) &spd[LPDDR3_SPD_PART_OFF];
*len = LPDDR3_SPD_PART_LEN;
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
break;
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
/* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */
lib/spd_bin: Correct LPDDR3 SPD information Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07 06:55:33 +01:00
case SPD_DRAM_LPDDR3_JEDEC:
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
case SPD_DRAM_DDR4:
lib/spd_bin: Extend LPDDR4 SPD information Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-06 14:18:30 +01:00
case SPD_DRAM_LPDDR4:
lib/spd_bin: add LPDDR4X case to spd_get_name() Add case for LPDDR4x to spd_get_name(). BUG=b:169800932, b:168724473 TEST=none Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 01:37:01 +02:00
case SPD_DRAM_LPDDR4X:
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
*spd_name = (const char *) &spd[DDR4_SPD_PART_OFF];
*len = DDR4_SPD_PART_LEN;
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
break;
default:
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
*len = 0;
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
break;
}
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
}
void print_spd_info(uint8_t spd[])
{
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
const char *nameptr = NULL;
size_t len;
lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02 09:01:56 +02:00
int type = spd[SPD_DRAM_TYPE];
int banks = spd_get_banks(spd, type);
int capmb = spd_get_capmb(spd);
int rows = spd_get_rows(spd);
int cols = spd_get_cols(spd);
int ranks = spd_get_ranks(spd, type);
int devw = spd_get_devw(spd, type);
int busw = spd_get_busw(spd, type);
/* Module type */
printk(BIOS_INFO, "SPD: module type is %s\n",
spd_get_module_type_string(type));
/* Module Part Number */
lib/spd: respect spd memory part name override The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 02:08:00 +02:00
spd_get_name(spd, type, &nameptr, &len);
if (nameptr)
printk(BIOS_INFO, "SPD: module part number is %.*s\n", (int) len, nameptr);
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
printk(BIOS_INFO,
"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
banks, ranks, rows, cols, capmb);
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
devw, busw);
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
capmb / 8 * busw / devw * ranks);
}
}
int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index)
{
struct cbfsf fh;
uint32_t cbfs_type = CBFS_TYPE_SPD;
lib/spd_bin: Check return code & remove dead code Remove dead code to address CID 1366756 Control flow issues (DEADCODE) Add return value check to address CID 1366755 Error handling issues (CHECKED_RETURN) Found-by: Coverity Scan #1366755 Found-by: Coverity Scan #1366756 Change-Id: Id02f6915ec7c6a4abfce20332c55833683e52d77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17838 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 15:57:15 +01:00
if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0)
return -1;
lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26 16:13:14 +02:00
cbfs_file_data(spd_rdev, &fh);
return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE,
CONFIG_DIMM_SPD_SIZE);
}
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
#if CONFIG_DIMM_SPD_SIZE == 128
int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
{
const int SPD_CRC_HI = 127;
const int SPD_CRC_LO = 126;
cbfs: Simplify load/map API names, remove type arguments This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-05 01:52:08 +01:00
char *spd_file;
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
size_t spd_file_len = 0;
size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
cbfs: Simplify load/map API names, remove type arguments This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-05 01:52:08 +01:00
spd_file = cbfs_map("spd.bin", &spd_file_len);
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
if (!spd_file)
printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
if (spd_file_len < min_len)
printk(BIOS_EMERG, "Missing SPD data.");
if (!spd_file || spd_file_len < min_len)
return -1;
src/lib: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I5fa3f8e950e2f0c60bd0e8f030342dc8c0469299 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-11 00:23:24 +01:00
memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE),
CONFIG_DIMM_SPD_SIZE);
cbfs: Simplify load/map API names, remove type arguments This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-05 01:52:08 +01:00
cbfs_unmap(spd_file);
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
src/lib: Use tabs instead of spaces Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: switch and case should be at the same indent WARNING: Statements should start on a tabstop WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: suspect code indent for conditional statements WARNING: labels should not be indented TEST=Build and run on Galileo Gen2 Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10 01:21:34 +01:00
|| (buf[SPD_CRC_LO] != (crc & 0xff))
|| (buf[SPD_CRC_HI] != (crc >> 8))) {
src/lib: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I5fa3f8e950e2f0c60bd0e8f030342dc8c0469299 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-11 00:23:24 +01:00
printk(BIOS_WARNING,
"SPD CRC %02x%02x is invalid, should be %04x\n",
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
buf[SPD_CRC_LO] = crc & 0xff;
buf[SPD_CRC_HI] = crc >> 8;
u16 i;
printk(BIOS_WARNING, "\nDisplay the SPD");
for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
src/lib: Add space before ( Fix the following error detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I8953fecbe75136ff989c9e3cf6c5e155dcee3c3b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18698 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-09 03:02:24 +01:00
if ((i % 16) == 0x00)
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
printk(BIOS_WARNING, "\n%02x: ", i);
printk(BIOS_WARNING, "%02x ", buf[i]);
}
printk(BIOS_WARNING, "\n");
src/lib: Use tabs instead of spaces Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: switch and case should be at the same indent WARNING: Statements should start on a tabstop WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: suspect code indent for conditional statements WARNING: labels should not be indented TEST=Build and run on Galileo Gen2 Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10 01:21:34 +01:00
}
return 0;
ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-28 15:59:25 +01:00
}
#endif