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coreboot-kgpe-d16/src/lib/Kconfig

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reset: Provide new single-function reset API board_reset() replaces the existing common reset API. There is no common distinction between reset types across platforms, hence, common code could never decide which one to call. Currently only hard_reset() is used by common code. We replace these calls and provide a fall-back to the current hard_reset() implemen- tation. The fall-back will be removed along with hard_reset() after the transition of all boards. Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-05 23:40:21 +02:00
config MISSING_BOARD_RESET
bool
help
Selected by boards that don't provide a do_board_reset()
implementation. This activates a stub that logs the missing
board reset and halts execution.
Kconfig: Move libhwbase related options into lib/Kconfig More will follow so better move them where they are used. Also remove defaults and add dependencies to not clutter .config files up that don't have any of these options selected. Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-17 23:39:02 +02:00
config RAMSTAGE_ADA
bool
help
Selected by features that use Ada code in ramstage.
config RAMSTAGE_LIBHWBASE
bool
select RAMSTAGE_ADA
help
Selected by features that require `libhwbase` in ramstage.
lib/devicetree: Integrate flattened devicetree support * Adapt to coreboot coding style. * Use coreboot's endian conversion functions. * Fix header and header guards. * Get rid of unused functions. * Add Kconfig to build it on ramstage. * Replace size32 with ALIGN_UP and DIV_ROUND_UP. * Add NULL pointer checks * Convert constants to defines Required for Cavium's BDK and uImage FIT support. Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-03 09:57:33 +02:00
config FLATTENED_DEVICE_TREE
bool
help
Selected by features that require to parse and manipulate a flattened
devicetree in ramstage.
treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFS The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-07 14:26:09 +02:00
config HAVE_SPD_IN_CBFS
src/Kconfig: Move DRAM section to src/lib/Kconfig These Kconfigs are mostly used in src/lib/. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32882 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-19 11:49:27 +02:00
bool
help
If enabled, add support for adding spd.hex files in cbfs as spd.bin
lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN SMBus code is linked unconditionally since commit 0e3c59e. This change drops that obsolete part from the help text. Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-07 13:26:51 +02:00
and locating it runtime to load SPD.
src/Kconfig: Move DRAM section to src/lib/Kconfig These Kconfigs are mostly used in src/lib/. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32882 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-19 11:49:27 +02:00
config DIMM_MAX
int
default 4
help
Total number of memory DIMM slots available on motherboard.
It is multiplication of number of channel to number of DIMMs per
channel
config DIMM_SPD_SIZE
int
default 256
help
Total SPD size that will be used for DIMM.
Ex: DDR3 256, DDR4 512.
config SPD_READ_BY_WORD
bool
src/lib: Add Kconfig option for SPD cache in FMAP Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 21:30:15 +01:00
config SPD_CACHE_IN_FMAP
bool
default n
help
Enables capability to cache DIMM SPDs in a dedicated FMAP region
to speed loading of SPD data. Currently requires board-level
romstage implementation to read/write/utilize cached SPD data.
When the default FMAP is used, will create a region named RW_SPD_CACHE
to store the cached SPD data.
config SPD_CACHE_FMAP_NAME
string
depends on SPD_CACHE_IN_FMAP
default "RW_SPD_CACHE"
help
Name of the FMAP region created in the default FMAP to cache SPD data.
Kconfig: Move libhwbase related options into lib/Kconfig More will follow so better move them where they are used. Also remove defaults and add dependencies to not clutter .config files up that don't have any of these options selected. Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-17 23:39:02 +02:00
if RAMSTAGE_LIBHWBASE
config HWBASE_DYNAMIC_MMIO
def_bool y
lib: Prepare for libhwbase' generated config file Add new libhwbase options and add a class for files generated during build. This follows the same pattern as for libgfxinit. Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-17 23:42:33 +02:00
config HWBASE_DEFAULT_MMCONF
hex
default MMCONF_BASE_ADDRESS
config HWBASE_DIRECT_PCIDEV
def_bool y
Kconfig: Move libhwbase related options into lib/Kconfig More will follow so better move them where they are used. Also remove defaults and add dependencies to not clutter .config files up that don't have any of these options selected. Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-17 23:39:02 +02:00
endif
lib/fmap: Disable pre-RAM cache for FSP 1.0 Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18 22:01:06 +01:00
config NO_FMAP_CACHE
bool
help
If your platform really doesn't want to use an FMAP cache (e.g. due to
space constraints), you can select this to disable warnings and save
a bit more code.
espi: Add support for debug helper to print slave capabilities This change adds a Kconfig option to enable eSPI debugging that pulls in a helper function to print slave capabilities. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I8ff250fe85dfa9370bf93ce3c7e2de5c069bf9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-11 21:11:27 +02:00
config ESPI_DEBUG
bool
help
This option enables eSPI library helper functions for displaying debug
information.
cbfs: Add metadata cache This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-12 02:09:39 +01:00
config NO_CBFS_MCACHE
bool
help
Disables the CBFS metadata cache. This means that your platform does
not need to provide a CBFS_MCACHE section in memlayout and can save
the associated CAR/SRAM size. In that case every single CBFS file
lookup must re-read the same CBFS directory entries from flash to find
the respective file.
config CBFS_MCACHE_RW_PERCENTAGE
int
depends on VBOOT && !NO_CBFS_MCACHE
default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only
default 50
help
The amount of the CBFS_MCACHE area that's used for the RW CBFS, in
percent from 0 to 100. The remaining area will be used for the RO
CBFS. Default is an even 50/50 split. When VBOOT is disabled, this
will automatically be 0 (meaning the whole MCACHE is used for RO).