2016-07-20 17:58:58 +02:00
|
|
|
/*
|
|
|
|
* This file is part of the coreboot project.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2013 Google Inc.
|
|
|
|
* Copyright (C) 2015-2016 Intel Corp.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; version 2 of the License.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
2018-10-26 15:06:33 +02:00
|
|
|
|
2016-07-20 17:58:58 +02:00
|
|
|
#include <fsp/util.h>
|
|
|
|
#include <soc/ramstage.h>
|
|
|
|
|
2017-03-14 01:13:39 +01:00
|
|
|
void fsp_silicon_init(bool s3wake)
|
2016-07-20 17:58:58 +02:00
|
|
|
{
|
|
|
|
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
|
|
|
|
intel_silicon_init();
|
|
|
|
else
|
2017-03-14 01:13:39 +01:00
|
|
|
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
|
2016-07-20 17:58:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void soc_silicon_init_params(SILICON_INIT_UPD *upd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
|
|
|
|
SILICON_INIT_UPD *new)
|
|
|
|
{
|
|
|
|
}
|