e9a0130879
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
35 lines
967 B
C
35 lines
967 B
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <fsp/util.h>
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#include <soc/ramstage.h>
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void fsp_silicon_init(bool s3wake)
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{
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if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
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intel_silicon_init();
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else
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fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
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}
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void soc_silicon_init_params(SILICON_INIT_UPD *upd)
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{
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
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SILICON_INIT_UPD *new)
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{
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}
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