2019-04-22 22:55:16 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010-2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2019-04-23 00:04:13 +02:00
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#ifndef __PICASSO_CHIP_H__
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#define __PICASSO_CHIP_H__
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2019-04-22 22:55:16 +02:00
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#include <stddef.h>
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#include <stdint.h>
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#include <commonlib/helpers.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/i2c.h>
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#include <arch/acpi_device.h>
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#define MAX_NODES 1
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#define MAX_DRAM_CH 1
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#define MAX_DIMMS_PER_CH 2
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#define STONEY_I2C_DEV_MAX 4
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struct soc_amd_stoneyridge_config {
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u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
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enum {
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DRAM_CONTENTS_KEEP,
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DRAM_CONTENTS_CLEAR
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} dram_clear_on_reset;
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enum {
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/* Do not enable UMA in the system. */
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UMAMODE_NONE,
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/* Enable UMA with a specific size. */
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UMAMODE_SPECIFIED_SIZE,
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/* Let AGESA determine the proper size. Non-legacy requires
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* the resolution to be specified PLATFORM_CONFIGURATION */
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UMAMODE_AUTO_LEGACY,
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UMAMODE_AUTO_NON_LEGACY,
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} uma_mode;
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/* Used if UMAMODE_SPECIFIED_SIZE is set. */
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size_t uma_size;
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/*
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* If sb_reset_i2c_slaves() is called, this devicetree register
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* defines which I2C SCL will be toggled 9 times at 100 KHz.
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* For example, should we need I2C0 and I2C3 have their slave
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* devices reseted by toggling SCL, use:
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*
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* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
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*/
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
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u8 stapm_percent;
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u32 stapm_time_ms;
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u32 stapm_power_mw;
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/*
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* This specifies the LVDS/eDP power-up sequence time for the delay
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* between VaryBL and BLON.
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* 0 - Use the VBIOS default (default). The video BIOS default is 32ms.
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* n - Values other than zero specify a setting of (4 * n) milliseconds
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* time delay.
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*/
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u8 lvds_poseq_varybl_to_blon;
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u8 lvds_poseq_blon_to_varybl;
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};
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typedef struct soc_amd_stoneyridge_config config_t;
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extern struct device_operations pci_domain_ops;
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2019-04-23 00:04:13 +02:00
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#endif /* __PICASSO_CHIP_H__ */
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