coreboot-kgpe-d16/src/soc/ucb/riscv/Kconfig

config SOC_UCB_RISCV
	select ARCH_RISCV
	select ARCH_BOOTBLOCK_RISCV
	select ARCH_ROMSTAGE_RISCV
	select ARCH_RAMSTAGE_RISCV
	select DYNAMIC_CBMEM
	bool
	default n

if SOC_UCB_RISCV

endif
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00			`config SOC_UCB_RISCV`
			`select ARCH_RISCV`
			`select ARCH_BOOTBLOCK_RISCV`
			`select ARCH_ROMSTAGE_RISCV`
			`select ARCH_RAMSTAGE_RISCV`
UCB RISCV: Switch to DYNAMIC_CBMEM Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> 2014-12-01 19:35:43 +01:00			`select DYNAMIC_CBMEM`
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00			`bool`
			`default n`

			`if SOC_UCB_RISCV`

			`endif`