2012-12-08 02:24:06 +01:00
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#ifndef STDDEF_H
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#define STDDEF_H
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2003-04-22 21:02:15 +02:00
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typedef long ptrdiff_t;
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2012-05-14 22:21:08 +02:00
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#ifndef __SIZE_TYPE__
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#define __SIZE_TYPE__ unsigned long
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#endif
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typedef __SIZE_TYPE__ size_t;
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2013-05-02 23:02:28 +02:00
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/* There is a GCC macro for a size_t type, but not
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* for a ssize_t type. Below construct tricks GCC
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* into making __SIZE_TYPE__ signed.
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*/
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#define unsigned signed
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typedef __SIZE_TYPE__ ssize_t;
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#undef unsigned
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2003-04-22 21:02:15 +02:00
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typedef int wchar_t;
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typedef unsigned int wint_t;
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2004-10-14 22:54:17 +02:00
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#define NULL ((void *)0)
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2003-04-22 21:02:15 +02:00
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2013-03-16 04:17:26 +01:00
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/* Standard units. */
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#define KiB (1<<10)
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#define MiB (1<<20)
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#define GiB (1<<30)
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/* Could we ever run into this one? I hope we get this much memory! */
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#define TiB (1<<40)
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2003-04-22 21:02:15 +02:00
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#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
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2013-12-10 02:46:22 +01:00
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#define check_member(structure, member, offset) _Static_assert( \
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offsetof(struct structure, member) == offset, \
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"`struct " #structure "` offset for `" #member "` is not " #offset )
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Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
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#ifdef __PRE_RAM__
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#define ROMSTAGE_CONST const
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#else
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#define ROMSTAGE_CONST
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#endif
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2012-12-08 02:24:06 +01:00
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#endif /* STDDEF_H */
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