GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/soc/intel/apollolake/pmutil.c

368 lines
8.6 KiB
C
Raw Normal View History

soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
#define __SIMPLE_DEVICE__
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <arch/io.h>
#include <console/console.h>
#include <rules.h>
#include <device/pci_def.h>
#include <soc/iomap.h>
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
#include <soc/pci_devs.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <soc/pm.h>
#include <device/device.h>
#include <device/pci.h>
soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26 18:00:44 +02:00
#include <vendorcode/google/chromeos/vboot_common.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
static uintptr_t read_pmc_mmio_bar(void)
{
uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0);
return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
static void print_num_status_bits(int num_bits, uint32_t status,
const char * const bit_names[])
{
int i;
if (!status)
return;
for (i = num_bits - 1; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
else
printk(BIOS_DEBUG, "BIT%d ", i);
}
}
}
static uint32_t print_smi_status(uint32_t smi_sts)
{
static const char * const smi_sts_bits[] = {
soc/intel/apollolake: add SMI status bit definitons and use them Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-11 01:01:45 +02:00
[BIOS_SMI_STS] = "BIOS",
[LEGACY_USB_SMI_STS] = "LEGACY USB",
[SLP_SMI_STS] = "SLP_SMI",
[APM_SMI_STS] = "APM",
[SWSMI_TMR_SMI_STS] = "SWSMI_TMR",
soc/intel/apollolake: provide fake PM1 SMI status bit It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11 01:04:21 +02:00
[FAKE_PM1_SMI_STS] = "PM1",
soc/intel/apollolake: add SMI status bit definitons and use them Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-11 01:01:45 +02:00
[GPIO_SMI_STS]= "GPIO_SMI",
[GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI",
[MC_SMI_STS] = "MCSMI",
[TCO_SMI_STS] = "TCO",
[PERIODIC_SMI_STS] = "PERIODIC",
[SERIRQ_SMI_STS] = "SERIRQ",
[SMBUS_SMI_STS] = "SMBUS_SMI",
[XHCI_SMI_STS] = "XHCI",
[HSMBUS_SMI_STS] = "HOST_SMBUS",
[SCS_SMI_STS] = "SCS",
[PCIE_SMI_STS] = "PCI_EXP_SMI",
[SCC2_SMI_STS] = "SCC2",
[SPI_SSMI_STS] = "SPI_SSMI",
[SPI_SMI_STS] = "SPI",
[PMC_OCP_SMI_STS] = "OCP_CSE",
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
};
if (!smi_sts)
return 0;
printk(BIOS_DEBUG, "SMI_STS: ");
print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
printk(BIOS_DEBUG, "\n");
return smi_sts;
}
static uint32_t reset_smi_status(void)
{
uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS);
outl(smi_sts, ACPI_PMIO_BASE + SMI_STS);
return smi_sts;
}
uint32_t clear_smi_status(void)
{
soc/intel/apollolake: provide fake PM1 SMI status bit It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11 01:04:21 +02:00
uint32_t sts = reset_smi_status();
/*
* Check for power button status if nothing else is indicating an SMI
* and SMIs aren't turned into SCIs. Apparently, there is no PM1 status
* bit in the SMI status register. That makes things difficult for
* determining if the power button caused an SMI.
*/
if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) {
uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
/* Fake PM1 status bit if power button pressed. */
if (pm1_sts & PWRBTN_STS)
sts |= (1 << FAKE_PM1_SMI_STS);
}
return print_smi_status(sts);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
uint32_t get_smi_en(void)
{
return inl(ACPI_PMIO_BASE + SMI_EN);
}
void enable_smi(uint32_t mask)
{
uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
smi_en |= mask;
outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
}
void disable_smi(uint32_t mask)
{
uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
smi_en &= ~mask;
outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
}
void enable_pm1_control(uint32_t mask)
{
uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
pm1_cnt |= mask;
outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
}
void disable_pm1_control(uint32_t mask)
{
uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
pm1_cnt &= ~mask;
outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
}
static uint16_t reset_pm1_status(void)
{
uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS);
return pm1_sts;
}
static uint16_t print_pm1_status(uint16_t pm1_sts)
{
static const char * const pm1_sts_bits[] = {
[0] = "TMROF",
[5] = "GBL",
[8] = "PWRBTN",
[10] = "RTC",
[11] = "PRBTNOR",
[13] = "USB",
[14] = "PCIEXPWAK",
[15] = "WAK",
};
if (!pm1_sts)
return 0;
printk(BIOS_SPEW, "PM1_STS: ");
print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
printk(BIOS_SPEW, "\n");
return pm1_sts;
}
uint16_t clear_pm1_status(void)
{
return print_pm1_status(reset_pm1_status());
}
void enable_pm1(uint16_t events)
{
outw(events, ACPI_PMIO_BASE + PM1_EN);
}
static uint32_t print_tco_status(uint32_t tco_sts)
{
static const char * const tco_sts_bits[] = {
[3] = "TIMEOUT",
[17] = "SECOND_TO",
};
if (!tco_sts)
return 0;
printk(BIOS_DEBUG, "TCO_STS: ");
print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
printk(BIOS_DEBUG, "\n");
return tco_sts;
}
static uint32_t reset_tco_status(void)
{
uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT);
outl(tco_sts, ACPI_PMIO_BASE + TCO_STS);
return tco_sts & tco_en;
}
uint32_t clear_tco_status(void)
{
return print_tco_status(reset_tco_status());
}
void enable_gpe(uint32_t mask)
{
uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
gpe0a_en |= mask;
outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
}
void disable_gpe(uint32_t mask)
{
uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
gpe0a_en &= ~mask;
outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
}
void disable_all_gpe(void)
{
disable_gpe(~0);
}
static uint32_t reset_gpe_status(void)
{
uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0));
outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0));
return gpe_sts;
}
static uint32_t print_gpe_sts(uint32_t gpe_sts)
{
static const char * const gpe_sts_bits[] = {
[0] = "PCIE_SCI",
[2] = "SWGPE",
[3] = "PCIE_WAKE0",
[4] = "PUNIT",
[6] = "PCIE_WAKE1",
[7] = "PCIE_WAKE2",
[8] = "PCIE_WAKE3",
[9] = "PCI_EXP",
[10] = "BATLOW",
[11] = "CSE_PME",
[12] = "XDCI_PME",
[13] = "XHCI_PME",
[14] = "AVS_PME",
[15] = "GPIO_TIER1_SCI",
[16] = "SMB_WAK",
[17] = "SATA_PME",
};
if (!gpe_sts)
return gpe_sts;
printk(BIOS_DEBUG, "GPE0a_STS: ");
print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
printk(BIOS_DEBUG, "\n");
return gpe_sts;
}
uint32_t clear_gpe_status(void)
{
return print_gpe_sts(reset_gpe_status());
}
void clear_pmc_status(void)
{
uint32_t prsts;
uint32_t gen_pmcon1;
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
prsts = read32((void *)(pmc_bar0 + PRSTS));
gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
/* Clear the status bits. The RPS field is cleared on a 0 write. */
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((void *)(pmc_bar0 + PRSTS), prsts);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
/* Return 0, 3, or 5 to indicate the previous sleep state. */
int chipset_prev_sleep_state(struct chipset_power_state *ps)
{
/* Default to S0. */
int prev_sleep_state = SLEEP_STATE_S0;
if (ps->pm1_sts & WAK_STS) {
switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
case SLP_TYP_S3:
prev_sleep_state = SLEEP_STATE_S3;
break;
#endif
case SLP_TYP_S5:
prev_sleep_state = SLEEP_STATE_S5;
break;
}
}
return prev_sleep_state;
}
/* returns prev_sleep_state */
int fill_power_state(struct chipset_power_state *ps)
{
int i;
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN);
ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1));
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
ps->prev_sleep_state = chipset_prev_sleep_state(ps);
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
ps->prsts, ps->tco_sts);
printk(BIOS_DEBUG,
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS));
for (i=0; i < GPE0_REG_MAX; i++) {
ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
}
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps->prev_sleep_state;
}
soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26 18:00:44 +02:00
int vboot_platform_is_resuming(void)
{
int typ;
if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS))
return 0;
typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
return typ == SLP_TYP_S3;
}
Reference in a new issue Copy permalink