2003-04-22 21:02:15 +02:00
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#include <console/console.h>
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#include <arch/pirq_routing.h>
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#include <string.h>
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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#include <device/pci.h>
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2003-04-22 21:02:15 +02:00
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2004-03-23 18:41:15 +01:00
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#if (DEBUG==1 && HAVE_PIRQ_TABLE==1)
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2004-06-07 12:25:42 +02:00
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static void check_pirq_routing_table(struct irq_routing_table *rt)
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2003-04-22 21:02:15 +02:00
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{
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2004-06-07 12:25:42 +02:00
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uint8_t *addr = (uint8_t *)rt;
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uint8_t sum=0;
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2003-04-22 21:02:15 +02:00
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int i;
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2009-01-20 20:21:47 +01:00
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printk_info("Checking Interrupt Routing Table consistency...\n");
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2003-04-22 21:02:15 +02:00
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2003-04-24 08:56:37 +02:00
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#if defined(IRQ_SLOT_COUNT)
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2004-06-07 12:25:42 +02:00
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if (sizeof(struct irq_routing_table) != rt->size) {
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2009-01-20 20:21:47 +01:00
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printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
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2004-06-07 12:25:42 +02:00
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sizeof(struct irq_routing_table),
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rt->size
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2004-04-15 19:33:21 +02:00
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);
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2004-06-07 12:25:42 +02:00
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rt->size=sizeof(struct irq_routing_table);
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2003-04-22 21:02:15 +02:00
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}
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#endif
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for (i = 0; i < rt->size; i++)
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sum += addr[i];
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2009-01-20 20:21:47 +01:00
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printk_debug("%s(): Interrupt Routing Table located at 0x%p.\n",
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2005-01-19 15:06:41 +01:00
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__FUNCTION__, addr);
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2003-04-22 21:02:15 +02:00
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2003-04-25 04:02:25 +02:00
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sum = rt->checksum - sum;
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2003-04-22 21:02:15 +02:00
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if (sum != rt->checksum) {
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2009-01-20 20:21:47 +01:00
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printk_warning("Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n",
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rt->checksum, sum);
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2003-10-28 18:02:10 +01:00
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rt->checksum = sum;
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2003-04-22 21:02:15 +02:00
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}
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if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
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2004-06-07 12:25:42 +02:00
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rt->size % 16 ) {
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2009-01-20 20:21:47 +01:00
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printk_warning("Interrupt Routing Table not valid.\n");
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2003-04-22 21:02:15 +02:00
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return;
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}
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sum = 0;
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for (i=0; i<rt->size; i++)
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sum += addr[i];
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2009-01-20 20:21:47 +01:00
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/* We're manually fixing the checksum above. This warning can probably
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* never happen because if the target location is read-only this
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* function would have bailed out earlier.
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*/
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2003-04-22 21:02:15 +02:00
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if (sum) {
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2009-01-20 20:21:47 +01:00
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printk_warning("Checksum error in Interrupt Routing Table "
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"could not be fixed.\n");
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2003-04-22 21:02:15 +02:00
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}
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printk_info("done.\n");
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}
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2004-06-07 12:25:42 +02:00
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static int verify_copy_pirq_routing_table(unsigned long addr)
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2003-04-22 21:02:15 +02:00
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{
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int i;
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2003-04-24 08:56:37 +02:00
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uint8_t *rt_orig, *rt_curr;
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2003-04-22 21:02:15 +02:00
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2003-04-24 08:56:37 +02:00
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rt_curr = (uint8_t*)addr;
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rt_orig = (uint8_t*)&intel_irq_routing_table;
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2009-01-20 20:21:47 +01:00
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printk_info("Verifing copy of Interrupt Routing Table at 0x%08x... ", addr);
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2003-04-22 21:02:15 +02:00
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for (i = 0; i < intel_irq_routing_table.size; i++) {
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if (*(rt_curr + i) != *(rt_orig + i)) {
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printk_info("failed\n");
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return -1;
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}
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}
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2004-01-26 11:54:44 +01:00
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printk_info("done\n");
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2004-06-07 12:25:42 +02:00
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check_pirq_routing_table((struct irq_routing_table *)addr);
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2003-04-22 21:02:15 +02:00
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return 0;
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}
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#else
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#define verify_copy_pirq_routing_table(addr)
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#endif
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2004-03-23 18:41:15 +01:00
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#if HAVE_PIRQ_TABLE==1
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2003-04-22 21:02:15 +02:00
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unsigned long copy_pirq_routing_table(unsigned long addr)
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{
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/* Align the table to be 16 byte aligned. */
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addr += 15;
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addr &= ~15;
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/* This table must be betweeen 0xf0000 & 0x100000 */
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2009-01-20 20:21:47 +01:00
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printk_info("Copying Interrupt Routing Table to 0x%08x... ", addr);
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2003-04-22 21:02:15 +02:00
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memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
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printk_info("done.\n");
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verify_copy_pirq_routing_table(addr);
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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pirq_routing_irqs(addr);
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2003-04-22 21:02:15 +02:00
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return addr + intel_irq_routing_table.size;
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}
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2004-03-23 18:41:15 +01:00
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#endif
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
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void pirq_routing_irqs(unsigned long addr)
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{
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int i, j, k, num_entries;
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unsigned char irq_slot[4];
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unsigned char pirq[4] = {0, 0, 0, 0};
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struct irq_routing_table *pirq_tbl;
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device_t pdev;
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pirq_tbl = (struct irq_routing_table *)(addr);
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num_entries = (pirq_tbl->size - 32) / 16;
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/* Set PCI IRQs. */
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for (i = 0; i < num_entries; i++) {
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2009-01-20 20:21:47 +01:00
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printk_debug("PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i,
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++) {
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int link = pirq_tbl->slots[i].irq[j].link;
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2008-04-07 19:49:57 +02:00
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int bitmap = pirq_tbl->slots[i].irq[j].bitmap;
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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int irq = 0;
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printk_debug("INT: %c link: %x bitmap: %x ",
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'A' + j, link, bitmap);
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if (!bitmap|| !link || link > 4) {
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printk_debug("not routed\n");
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irq_slot[j] = irq;
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continue;
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}
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/* yet not routed */
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if (!pirq[link - 1]) {
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2008-10-23 00:20:48 +02:00
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for (k = 2; k <= 15; k++) {
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Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:59:27 +01:00
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if (!((bitmap >> k) & 1))
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continue;
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irq = k;
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/* yet not routed */
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if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq)
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break;
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}
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if (irq)
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pirq[link - 1] = irq;
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}
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else
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irq = pirq[link - 1];
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printk_debug("IRQ: %d\n", irq);
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irq_slot[j] = irq;
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}
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/* Bus, device, slots IRQs for {A,B,C,D}. */
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pci_assign_irqs(pirq_tbl->slots[i].bus,
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|
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pirq_tbl->slots[i].devfn >> 3, irq_slot);
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|
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}
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printk_debug("PIRQ1: %d\n", pirq[0]);
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printk_debug("PIRQ2: %d\n", pirq[1]);
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printk_debug("PIRQ3: %d\n", pirq[2]);
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printk_debug("PIRQ4: %d\n", pirq[3]);
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pirq_assign_irqs(pirq);
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|
|
|
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}
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#endif
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