2011-04-20 11:12:17 +02:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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chip northbridge/intel/i945
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device lapic_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device lapic 0 on end
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end
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end
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2013-02-12 23:17:15 +01:00
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device domain 0 on
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2011-04-20 11:12:17 +02:00
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device pci 00.0 on # Host bridge
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subsystemid 0x17aa 0x2015
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end
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device pci 01.0 on # PCI-e
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device pci 00.0 on # VGA
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subsystemid 0x17aa 0x20a4
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end
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end
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device pci 02.0 on # GMA Graphics controller
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subsystemid 0x17aa 0x201a
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end
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device pci 02.1 on # display controller
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subsystemid 0x17aa 0x201a
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end
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "2"
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register "gpi12_routing" = "2"
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register "gpi8_routing" = "2"
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2011-10-27 13:10:14 +02:00
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x01"
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2011-04-20 11:12:17 +02:00
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register "gpe0_en" = "0x11000006"
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2011-06-23 19:12:25 +02:00
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register "alt_gp_smi_en" = "0x1000"
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2011-04-20 11:12:17 +02:00
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2011-10-23 16:36:22 +02:00
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register "c4onc3_enable" = "1"
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2011-04-20 11:12:17 +02:00
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device pci 1b.0 on # Audio Cnotroller
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subsystemid 0x17aa 0x2010
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end
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device pci 1c.0 on # Ethernet
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subsystemid 0x17aa 0x2001
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end
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device pci 1c.1 on end # WLAN
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device pci 1d.0 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.1 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.2 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.3 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.7 on # USB2 EHCI
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subsystemid 0x17aa 0x200b
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end
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device pci 1e.0 on # PCI Bridge
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chip southbridge/ti/pci1x2x
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device pci 00.0 on
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subsystemid 0x17aa 0x2012
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end
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register "scr" = "0x0844d070"
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register "mrr" = "0x01d01002"
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end
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end
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x17aa 0x2009
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa6"
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register "config1" = "0x05"
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register "config2" = "0xa0"
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2011-07-11 14:58:48 +02:00
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register "config3" = "0x01"
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2011-04-20 11:12:17 +02:00
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register "beepmask0" = "0xfe"
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register "beepmask1" = "0x96"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xf4"
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2011-06-23 11:59:48 +02:00
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register "event5_enable" = "0x3f"
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2011-04-20 11:12:17 +02:00
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register "event6_enable" = "0x80"
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2011-06-23 11:59:48 +02:00
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x01"
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register "event9_enable" = "0xff"
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2011-06-23 13:41:55 +02:00
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register "eventa_enable" = "0xff"
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register "eventb_enable" = "0xff"
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2011-06-23 11:59:48 +02:00
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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2011-04-28 11:29:06 +02:00
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register "eventc_enable" = "0x3c"
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2011-04-20 11:12:17 +02:00
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register "wlan_enable" = "0x01"
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register "trackpoint_enable" = "0x03"
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end
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chip superio/nsc/pc87382
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device pnp 164e.2 on # IR
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io 0x60 = 0x2f8
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end
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device pnp 164e.3 off # Serial Port
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io 0x60 = 0x3f8
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end
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device pnp 164e.7 on # GPIO
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io 0x60 = 0x1680
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end
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device pnp 164e.19 on # DLPC
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io 0x60 = 0x164c
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end
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end
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chip superio/nsc/pc87384
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device pnp 2e.0 off #FDC
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x3bc
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Serial Port / IR
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io 0x60 = 0x2f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Serial Port
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.7 on # GPIO
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io 0x60 = 0x1620
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end
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device pnp 2e.a off # WDT
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end
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end
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end
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2011-04-27 21:47:49 +02:00
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device pci 1f.1 on # IDE
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2011-04-20 11:12:17 +02:00
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subsystemid 0x17aa 0x200c
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end
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device pci 1f.2 on # SATA
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subsystemid 0x17aa 0x200d
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x17aa 0x200f
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2011-10-23 15:54:31 +02:00
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chip drivers/ics/954309
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register "reg0" = "0x2e"
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register "reg1" = "0xf7"
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register "reg2" = "0x3c"
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register "reg3" = "0x20"
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register "reg4" = "0x01"
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register "reg5" = "0x00"
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register "reg6" = "0x1b"
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register "reg7" = "0x01"
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register "reg8" = "0x54"
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register "reg9" = "0xff"
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register "reg10" = "0xff"
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register "reg11" = "0x07"
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device i2c 69 on end
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end
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2011-04-20 11:12:17 +02:00
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end
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end
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end
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end
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