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sconfig: rename pci_domain -> domain 

The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer 2013-02-12 14:17:15 -08:00 committed by Ronald G. Minnich
parent dc8259ce1d
commit 4aff4458f5
230 changed files with 393 additions and 393 deletions
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4
documentation/Kconfig.tex
View File

@ -163,7 +163,7 @@ Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason i
is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
BIOSes) that the BSP be CPU 0; any CPU will do.
\begin{verbatim}
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
@ -338,7 +338,7 @@ That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much he
\end{verbatim}
\begin{verbatim}
end #pci_domain
end # domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all

2
src/arch/x86/boot/mpspec.c
View File

@ -502,7 +502,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr)
break;
}
if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) {
if (parent->path.type == DEVICE_PATH_DOMAIN) {
printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev));
break;
}

2
src/cpu/amd/sc520/sc520.c
View File

@ -186,7 +186,7 @@ static void enable_dev(struct device *dev)
{
printk(BIOS_SPEW, "%s\n", __func__);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}

8
src/device/device.c
View File

@ -994,7 +994,7 @@ void dev_configure(void)
/* Compute resources for all domains. */
for (child = root->link_list->children; child; child = child->sibling) {
if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
if (!(child->path.type == DEVICE_PATH_DOMAIN))
continue;
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)
@ -1019,7 +1019,7 @@ void dev_configure(void)
/* For all domains. */
for (child = root->link_list->children; child; child=child->sibling)
if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
if (child->path.type == DEVICE_PATH_DOMAIN)
avoid_fixed_resources(child);
/*
@ -1027,7 +1027,7 @@ void dev_configure(void)
* the highest address managable.
*/
for (child = root->link_list->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI_DOMAIN)
if (child->path.type != DEVICE_PATH_DOMAIN)
continue;
for (res = child->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_MEM) ||
@ -1040,7 +1040,7 @@ void dev_configure(void)
/* Store the computed resource allocations into device registers ... */
printk(BIOS_INFO, "Setting resources...\n");
for (child = root->link_list->children; child; child = child->sibling) {
if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
if (!(child->path.type == DEVICE_PATH_DOMAIN))
continue;
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)

10
src/device/device_util.c
View File

@ -205,9 +205,9 @@ const char *dev_path(device_t dev)
sprintf(buffer, "IOAPIC: %02x",
dev->path.ioapic.ioapic_id);
break;
case DEVICE_PATH_PCI_DOMAIN:
sprintf(buffer, "PCI_DOMAIN: %04x",
dev->path.pci_domain.domain);
case DEVICE_PATH_DOMAIN:
sprintf(buffer, "DOMAIN: %04x",
dev->path.domain.domain);
break;
case DEVICE_PATH_APIC_CLUSTER:
sprintf(buffer, "APIC_CLUSTER: %01x",
@ -271,8 +271,8 @@ int path_eq(struct device_path *path1, struct device_path *path2)
case DEVICE_PATH_APIC:
equal = (path1->apic.apic_id == path2->apic.apic_id);
break;
case DEVICE_PATH_PCI_DOMAIN:
equal = (path1->pci_domain.domain == path2->pci_domain.domain);
case DEVICE_PATH_DOMAIN:
equal = (path1->domain.domain == path2->domain.domain);
break;
case DEVICE_PATH_APIC_CLUSTER:
equal = (path1->apic_cluster.cluster

6
src/include/device/path.h
View File

@ -8,14 +8,14 @@ enum device_path_type {
DEVICE_PATH_PNP,
DEVICE_PATH_I2C,
DEVICE_PATH_APIC,
DEVICE_PATH_PCI_DOMAIN,
DEVICE_PATH_DOMAIN,
DEVICE_PATH_APIC_CLUSTER,
DEVICE_PATH_CPU,
DEVICE_PATH_CPU_BUS,
DEVICE_PATH_IOAPIC,
};
struct pci_domain_path
struct domain_path
{
unsigned domain;
};
@ -74,7 +74,7 @@ struct device_path {
struct i2c_path i2c;
struct apic_path apic;
struct ioapic_path ioapic;
struct pci_domain_path pci_domain;
struct domain_path domain;
struct apic_cluster_path apic_cluster;
struct cpu_path cpu;
struct cpu_bus_path cpu_bus;

2
src/mainboard/a-trend/atc-6220/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/a-trend/atc-6240/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES

2
src/mainboard/abit/be6-ii_v2_0/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

4
src/mainboard/advansus/a785e-i/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -120,5 +120,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
end

2
src/mainboard/advantech/pcm-5820/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1 # Northbridge
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
chip southbridge/amd/cs5530 # Southbridge
device pci 12.0 on # ISA bridge

8
src/mainboard/amd/bimini_fam10/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -76,9 +76,9 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
# device pci_domain 0 on
# device domain 0 on
# chip northbridge/amd/amdfam10
# device pci 00.0 on end# northbridge
# device pci 00.0 on end
@ -90,7 +90,7 @@ chip northbridge/amd/amdfam10/root_complex
# device pci 00.4 on end
# device pci 00.5 on end
# end
# end #pci_domain
# end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name

2
src/mainboard/amd/db800/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536

4
src/mainboard/amd/dbm690t/devicetree.cb
View File

@ -14,7 +14,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3050 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
@ -117,6 +117,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.2 on end
device pci 18.3 on end
end #northbridge/amd/amdk8
end #pci_domain
end #domain
end #northbridge/amd/amdk8/root_complex

4
src/mainboard/amd/dinar/devicetree.cb
View File

@ -23,7 +23,7 @@ chip northbridge/amd/agesa/family15/root_complex
device lapic 0x20 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1705 inherit
chip northbridge/amd/agesa/family15 # CPU side of HT root complex
device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs
@ -98,6 +98,6 @@ chip northbridge/amd/agesa/family15/root_complex
device pci 18.4 on end
device pci 18.5 on end
end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family15/root_complex

4
src/mainboard/amd/inagua/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family14/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
@ -88,6 +88,6 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family14/root_complex

4
src/mainboard/amd/mahogany/devicetree.cb
View File

@ -14,7 +14,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
@ -117,5 +117,5 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.2 on end
device pci 18.3 on end
end #northbridge/amd/amdk8
end #pci_domain
end #domain
end #northbridge/amd/amdk8/root_complex

8
src/mainboard/amd/mahogany_fam10/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -110,9 +110,9 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.4 on end
# device pci 00.5 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
# device pci_domain 0 on
# device domain 0 on
# chip northbridge/amd/amdfam10
# device pci 00.0 on end# northbridge
# device pci 00.0 on end
@ -124,7 +124,7 @@ chip northbridge/amd/amdfam10/root_complex
# device pci 00.4 on end
# device pci 00.5 on end
# end
# end #pci_domain
# end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name

2
src/mainboard/amd/norwich/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536

4
src/mainboard/amd/parmer/devicetree.cb
View File

@ -24,7 +24,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
@ -86,5 +86,5 @@ chip northbridge/amd/agesa/family15tn/root_complex
}"
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
end #pci_domain
end #domain
end #chip northbridge/amd/agesa/family15tn/root_complex

4
src/mainboard/amd/persimmon/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family14/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
@ -152,5 +152,5 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family14/root_complex

4
src/mainboard/amd/pistachio/devicetree.cb
View File

@ -14,7 +14,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3050 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge, K8 HT Configuration
@ -76,6 +76,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
device pci 18.3 on end # K8 Miscellaneous Control
end #northbridge/amd/amdk8
end #pci_domain
end #domain
end #northbridge/amd/amdk8/root_complex

2
src/mainboard/amd/rumba/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/gx2
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536

4
src/mainboard/amd/serengeti_cheetah/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x2b80 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
@ -143,7 +143,7 @@ chip northbridge/amd/amdk8/root_complex
end
end #pci_domain
end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all

8
src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x2b80 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -118,9 +118,9 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.4 on end
# device pci 00.5 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
# device pci_domain 0 on
# device domain 0 on
# chip northbridge/amd/amdfam10
# device pci 00.0 on end# northbridge
# device pci 00.0 on end
@ -132,7 +132,7 @@ chip northbridge/amd/amdfam10/root_complex
# device pci 00.4 on end
# device pci 00.5 on end
# end
# end #pci_domain
# end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name

4
src/mainboard/amd/south_station/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family14/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
@ -100,6 +100,6 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.4 on end
device pci 18.5 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family14/root_complex

4
src/mainboard/amd/thatcher/devicetree.cb
View File

@ -24,7 +24,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
@ -101,5 +101,5 @@ chip northbridge/amd/agesa/family15tn/root_complex
}"
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
end #pci_domain
end #domain
end #chip northbridge/amd/agesa/family15tn/root_complex

8
src/mainboard/amd/tilapia_fam10/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -111,9 +111,9 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.4 on end
# device pci 00.5 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
# device pci_domain 0 on
# device domain 0 on
# chip northbridge/amd/amdfam10
# device pci 00.0 on end# northbridge
# device pci 00.0 on end
@ -125,7 +125,7 @@ chip northbridge/amd/amdfam10/root_complex
# device pci 00.4 on end
# device pci 00.5 on end
# end
# end #pci_domain
# end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name

4
src/mainboard/amd/torpedo/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family12/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1705 inherit
chip northbridge/amd/agesa/family12 # CPU side of HT root complex
chip northbridge/amd/agesa/family12 # PCI side of HT root complex
@ -85,6 +85,6 @@ chip northbridge/amd/agesa/family12/root_complex
device pci 18.6 on end
device pci 18.7 on end
end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family12/root_complex

4
src/mainboard/amd/union_station/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family14/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
@ -76,6 +76,6 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.4 on end
device pci 18.5 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family14/root_complex

4
src/mainboard/aopen/dxplplusu/devicetree.cb
View File

@ -28,7 +28,7 @@ chip northbridge/intel/e7505
end
end
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end # Chipset host controller
device pci 0.1 on end # Host RASUM controller
device pci 2.0 on # Hub interface B
@ -86,5 +86,5 @@ chip northbridge/intel/e7505
device pci 1f.5 on end # AC97 Audio
device pci 1f.6 off end # AC97 Modem
end # SB
end # PCI_DOMAIN
end # PCI domain
end

2
src/mainboard/arima/hdama/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x161f 0x3016 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge

2
src/mainboard/artecgroup/dbe61/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536

2
src/mainboard/asi/mb_5blgp/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1 # Northbridge
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
chip southbridge/amd/cs5530 # Southbridge
device pci 0f.0 on end # Ethernet

2
src/mainboard/asi/mb_5blmp/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1 # Northbridge
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end # Host bridge
chip southbridge/amd/cs5530 # Southbridge
device pci 0f.0 off end # Ethernet (Realtek RTL8139B)

4
src/mainboard/asrock/939a785gmh/devicetree.cb
View File

@ -15,7 +15,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
@ -127,6 +127,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.2 on end
device pci 18.3 on end
end #northbridge/amd/amdk8
end #pci_domain
end #domain
end #northbridge/amd/amdk8/root_complex

4
src/mainboard/asrock/e350m1/devicetree.cb
View File

@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family14/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
@ -128,6 +128,6 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
end #domain
end #northbridge/amd/agesa/family14/root_complex

2
src/mainboard/asus/a8n_e/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0x815a inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Link 0 == LDT 0

2
src/mainboard/asus/a8v-e_deluxe/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 1043 0 inherit
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge

2
src/mainboard/asus/a8v-e_se/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0 inherit
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge

2
src/mainboard/asus/dsbf/devicetree.cb
View File

@ -28,7 +28,7 @@ chip northbridge/intel/i5000
end
end
device pci_domain 0 on
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x1043 0x81db
end

2
src/mainboard/asus/k8v-x/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0 inherit
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge

2
src/mainboard/asus/m2n-e/devicetree.cb
View File

@ -24,7 +24,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0x8239 inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Link 0 == LDT 0

2
src/mainboard/asus/m2v-mx_se/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0 inherit
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge

2
src/mainboard/asus/m2v/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1043 0 inherit
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge

4
src/mainboard/asus/m4a78-em/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1043 0x83f1 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -102,5 +102,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end # chip northbridge
end #pci_domain
end #domain
end # northbridge/amd/amdfam10/root_complex

4
src/mainboard/asus/m4a785-m/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1043 0x83a2 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -102,5 +102,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end # chip northbridge
end #pci_domain
end #domain
end # northbridge/amd/amdfam10/root_complex

4
src/mainboard/asus/m4a785t-m/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1043 0x83a2 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -104,5 +104,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end # chip northbridge
end #pci_domain
end #domain
end # northbridge/amd/amdfam10/root_complex

4
src/mainboard/asus/m5a88-v/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id.
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -120,5 +120,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
end

2
src/mainboard/asus/mew-am/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i82810 # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
device pci 1.0 on end # Chipset Graphics Controller (CGC)
chip southbridge/intel/i82801ax # Southbridge

2
src/mainboard/asus/mew-vm/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/intel/i82810
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 on # Onboard Video
# device pci 1.0 on end

2
src/mainboard/asus/p2b-d/devicetree.cb
View File

@ -7,7 +7,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 1 on end # Local APIC of CPU 1
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/asus/p2b-ds/devicetree.cb
View File

@ -7,7 +7,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 1 on end # Local APIC of CPU 1
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/asus/p2b-f/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/asus/p2b-ls/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/asus/p2b/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/asus/p3b-f/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

4
src/mainboard/avalue/eax-785e/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -107,5 +107,5 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
end

2
src/mainboard/axus/tc320/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1 # Northbridge
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
chip southbridge/amd/cs5530 # Southbridge
device pci 12.0 on # ISA bridge

2
src/mainboard/azza/pt-6ibd/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/bachmann/ot200/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES

2
src/mainboard/bcom/winnet100/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1 # Northbridge
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
chip southbridge/amd/cs5530 # Southbridge
device pci 0f.0 on end # Ethernet (onboard)

2
src/mainboard/bcom/winnetp680/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/via/cn700 # Northbridge
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control

2
src/mainboard/bifferos/bifferboard/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/rdc/r8610
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
chip southbridge/rdc/r8610 # Southbridge
device pci 7.0 on end # SB

2
src/mainboard/biostar/m6tba/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

4
src/mainboard/broadcom/blast/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x161f 0x3050 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
@ -118,7 +118,7 @@ chip northbridge/amd/amdk8/root_complex
end
end #pci_domain
end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all

2
src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
device pci a.0 on end # NIC (onboard)

2
src/mainboard/digitallogic/adl855pc/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/intel/i855
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
device pci 1.0 on end
chip southbridge/intel/i82801dx

2
src/mainboard/digitallogic/msm586seg/devicetree.cb
View File

@ -1,5 +1,5 @@
chip cpu/amd/sc520
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
device pci 12.0 on end # enet
device pci 14.0 on end # 69000

2
src/mainboard/digitallogic/msm800sev/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536

2
src/mainboard/eaglelion/5bcm/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
chip southbridge/amd/cs5530
device pci 12.0 on

2
src/mainboard/ecs/p6iwp-fe/devicetree.cb
View File

@ -24,7 +24,7 @@ chip northbridge/intel/i82810 # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
device pci 1.0 on end # Chipset Graphics Controller (CGC)
chip southbridge/intel/i82801ax # Southbridge

2
src/mainboard/emulation/qemu-x86/devicetree.cb
View File

@ -1,5 +1,5 @@
chip mainboard/emulation/qemu-x86
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
chip southbridge/intel/i82371eb # southbridge

2
src/mainboard/emulation/qemu-x86/northbridge.c
View File

@ -138,7 +138,7 @@ static struct device_operations pci_domain_ops = {
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}

2
src/mainboard/getac/p470/devicetree.cb
View File

@ -27,7 +27,7 @@ chip northbridge/intel/i945
end
end
device pci_domain 0 on
device domain 0 on
device pci 00.0 on end # host bridge
# autodetect:
#device pci 01.0 off end # i945 PCIe root port

2
src/mainboard/gigabyte/ga-6bxc/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/gigabyte/ga-6bxe/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge

2
src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1039 0x1234 inherit
chip northbridge/amd/amdk8 #mc0
device pci 18.0 on

2
src/mainboard/gigabyte/m57sli/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
subsystemid 0x1022 0x2b80 inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Link 0 == LDT 0

4
src/mainboard/gigabyte/ma785gm/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -110,6 +110,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
end

4
src/mainboard/gigabyte/ma785gmt/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -110,6 +110,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end
device pci 18.4 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
end

4
src/mainboard/gigabyte/ma78gm/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
@ -110,6 +110,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.4 on end
# device pci 00.5 on end
end
end #pci_domain
end #domain
#for node 32 to node 63
end

2
src/mainboard/google/butterfly/devicetree.cb
View File

@ -33,7 +33,7 @@ chip northbridge/intel/sandybridge
end
end
device pci_domain 0 on
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # PCIe Bridge for discrete graphics
device pci 02.0 on end # vga controller

2
src/mainboard/google/parrot/devicetree.cb
View File

@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge
end
end
device pci_domain 0 on
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller

2
src/mainboard/hp/dl145_g1/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x1022 0x7460 inherit
chip northbridge/amd/amdk8
device pci 18.0 on end # link 0

4
src/mainboard/hp/dl145_g3/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdk8 # northbridge
device pci 18.0 on # devices on link 0
chip southbridge/broadcom/bcm21000 # HT2100
@ -81,7 +81,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.3 on end
end # amdk8
end #pci_domain
end #domain
end

4
src/mainboard/hp/dl165_g6_fam10/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdfam10 # northbridge
device pci 18.0 on end
device pci 18.0 on end
@ -84,7 +84,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.4 on end
end # amdfam10
end #pci_domain
end #domain
end

2
src/mainboard/hp/e_vectra_p2706t/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/intel/i82810 # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 on end # Onboard VGA
chip southbridge/intel/i82801ax # Southbridge

2
src/mainboard/ibase/mb899/devicetree.cb
View File

@ -6,7 +6,7 @@ chip northbridge/intel/i945
end
end
device pci_domain 0 on
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller

2
src/mainboard/ibm/e325/devicetree.cb
View File

@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1

2
src/mainboard/ibm/e326/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdk8/root_complex
end
end
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on end # LDT 0
device pci 18.0 on # LDT 1

2
src/mainboard/iei/juki-511p/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
chip southbridge/amd/cs5530

4
src/mainboard/iei/kino-780am2-fam10/devicetree.cb
View File

@ -5,7 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
device pci_domain 0 on
device domain 0 on
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
@ -66,6 +66,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.2 on end
device pci 18.3 on end
end
end #pci_domain
end #domain
end #root_complex

2
src/mainboard/iei/nova4899r/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/gx1
device pci_domain 0 on
device domain 0 on
device pci 0.0 on end
chip southbridge/amd/cs5530
device pci 0a.0 on end # ETH0

2
src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
View File

@ -1,5 +1,5 @@
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536

2
src/mainboard/iei/pm-lx-800-r11/devicetree.cb
View File

@ -20,7 +20,7 @@
##
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block

2
src/mainboard/iei/pm-lx2-800-r10/devicetree.cb
View File

@ -20,7 +20,7 @@
##
chip northbridge/amd/lx
device pci_domain 0 on
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block

2
src/mainboard/intel/d810e2cb/devicetree.cb
View File

@ -24,7 +24,7 @@ chip northbridge/intel/i82810 # Northbridge
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device domain 0 on # PCI domain
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
device pci 1.0 on end # Chipset Graphics Controller (CGC)
chip southbridge/intel/i82801bx # Southbridge

2
src/mainboard/intel/d945gclf/devicetree.cb
View File

@ -25,7 +25,7 @@ chip northbridge/intel/i945
end
end
device pci_domain 0 on
device domain 0 on
subsystemid 0x8086 0x464c inherit
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port

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