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coreboot-kgpe-d16/src/soc/intel/cannonlake/smihandler.c

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soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01 20:32:06 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-20 07:39:45 +01:00
* Copyright (C) 2017-2020 Intel Corporation.
soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01 20:32:06 +02:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/intel/cannonlake: Add SoC API to make use SMM common code Add SoC API to detect any illegal access to write into the BIOS located in the FWH. Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20 05:41:33 +01:00
#include <console/console.h>
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20 07:19:45 +01:00
#include <device/pci_def.h>
soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-20 07:39:45 +01:00
#include <intelblocks/cse.h>
soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01 20:32:06 +02:00
#include <intelblocks/smihandler.h>
soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-20 07:39:45 +01:00
#include <soc/soc_chip.h>
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20 07:19:45 +01:00
#include <soc/pci_devs.h>
soc/intel/cannonlake: Fill the SMI usage Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 23:51:12 +02:00
#include <soc/pm.h>
soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01 20:32:06 +02:00
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20 07:19:45 +01:00
/*
* Specific SOC SMI handler during ramstage finalize phase
*
* BIOS can't make CSME function disable as is due to POSTBOOT_SAI
* restriction in place from CNP chipset. Hence create SMI Handler to
* perform CSME function disabling logic during SMM mode.
*/
void smihandler_soc_at_finalize(void)
{
const struct soc_intel_cannonlake_config *config;
soc/intel: Replace config_of_path() with config_of_soc() The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-27 23:20:27 +02:00
config = config_of_soc();
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20 07:19:45 +01:00
soc/intel/{cml, whl}: Add option to skip HECI disable in SMM This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-04 10:46:02 +02:00
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
soc/intel/common/block: Move cse common functions into block/cse This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-17 14:58:26 +02:00
heci_disable();
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20 07:19:45 +01:00
}
soc/intel/cannonlake: Fill the SMI usage Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 23:51:12 +02:00
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01 20:32:06 +02:00
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
[GPIO_STS_BIT] = smihandler_southbridge_gpi,
[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
[MCSMI_STS_BIT] = smihandler_southbridge_mc,
[TCO_STS_BIT] = smihandler_southbridge_tco,
[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
};
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