41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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* Copyright (C) 2006-2010 coresystems GmbH
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* Copyright (C) 2015-2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <console/uart.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <rules.h>
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#include <soc/pci_devs.h>
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unsigned int uart_platform_refclk(void)
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{
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return 44236800;
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}
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uintptr_t uart_platform_base(int idx)
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{
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/* HSUART controller #1 (B0:D20:F5). */
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device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
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/* UART base address at BAR0(offset 0x10). */
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return (unsigned int) (pci_read_config32(dev,
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PCI_BASE_ADDRESS_0) & ~0xfff);
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}
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