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soc/intel/quark: Enable Serial Port 

Add the code to enable debug serial output using HSUART1:

*  Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
*  Note that the BIST value is always zero as validated in
   esram_init.inc
*  The initial TSC value is currently not saved!

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if serial output is present on HSUART1 at
   115200 baud, 8-bit, no parity

Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This commit is contained in:
Lee Leahy 2016-02-07 14:37:13 -08:00 committed by Martin Roth
parent 5d7df71cfe
commit 87df8d08d6
11 changed files with 316 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/soc/intel/quark/Kconfig
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@ -26,8 +26,37 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select SOC_INTEL_COMMON
select TSC_CONSTANT_RATE
select UDELAY_TSC
select USE_MARCH_586
#####
# Debug serial output
# The following options configure the debug serial port
#####
config ENABLE_BUILTIN_HSUART1
bool "Enable built-in HSUART1"
default y
select NO_UART_ON_SUPERIO
select DRIVERS_UART_8250MEM_32
help
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART1, which can be used for the debug console.
config TTYS0_BASE
hex "HSUART1 Base Address"
depends on ENABLE_BUILTIN_HSUART1
default 0xA0019000
help
Memory mapped MMIO of HSUART1.
config TTYS0_LCS
int
depends on ENABLE_BUILTIN_HSUART1
default 3
#####
# Debug support
# The following options provide debug support for the Quark coreboot
@ -64,6 +93,19 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT
help
Indicate that TempRamInit was successful.
#####
# ESRAM layout
# Specify the portion of the ESRAM for coreboot to use as its data area.
#####
config DCACHE_RAM_BASE
hex
default 0x80070000
config DCACHE_RAM_SIZE
hex
default 0x00008000
#####
# Flash layout
# Specify the size of the coreboot file system in the read-only

4
src/soc/intel/quark/Makefile.inc
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@ -19,8 +19,12 @@ subdirs-y += romstage
subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += memmap.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include

27
src/soc/intel/quark/include/soc/iomap.h Normal file
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@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _QUARK_IOMAP_H_
#define _QUARK_IOMAP_H_
/*
* Memory Mapped IO base addresses.
*/
/* UART MMIO */
#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
#endif /* _QUARK_IOMAP_H_ */

26
src/soc/intel/quark/include/soc/pci_devs.h Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _QUARK_PCI_DEVS_H_
#define _QUARK_PCI_DEVS_H_
/* IO Fabric 1 */
#define SIO1_DEV 0x14
# define HSUART1_DEV SIO1_DEV
# define HSUART1_FUNC 5
#endif /* _QUARK_PCI_DEVS_H_ */

29
src/soc/intel/quark/include/soc/romstage.h Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _QUARK_ROMSTAGE_H_
#define _QUARK_ROMSTAGE_H_
#if !defined(__PRE_RAM__)
#error "Don't include romstage.h from a ramstage compilation unit!"
#endif
#include <fsp/util.h>
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
#endif /* _QUARK_ROMSTAGE_H_ */

3
src/soc/intel/quark/romstage/Makefile.inc
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@ -15,3 +15,6 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
romstage-y += romstage.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c

41
src/soc/intel/quark/romstage/cache_as_ram.inc
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@ -115,7 +115,46 @@ CAR_init_done:
#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
/* Set up bootloader stack */
clrl %eax
movl %edx, %esp
/*
* eax: 0
* ebp: FSP_INFO_HEADER address
* ecx: Temp RAM base
* edx: Temp RAM top
* edi: BIST value
* esp: Top of stack in temp RAM
*/
/* Create cache_as_ram_params on stack */
pushl %edx /* bootloader CAR end */
pushl %ecx /* bootloader CAR begin */
pushl %ebp /* FSP_INFO_HEADER */
pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */
/* TODO: Locate 64-bits of storage for initial TSC value */
pushl $0 /* tsc[63:32] */
pushl $0 /* tsc[31:0] */
pushl %esp /* pointer to cache_as_ram_params */
/* Save FSP_INFO_HEADER location in ebx */
mov %ebp, %ebx
/* Coreboot assumes stack/heap region will be zero */
cld
movl %ecx, %edi
neg %ecx
/* Only clear up to current stack value. */
add %esp, %ecx
shrl $2, %ecx
xorl %eax, %eax
rep stosl
before_romstage:
post_code(0x2A)
/* Call cache_as_ram_main(struct cache_as_ram_params *) */
call cache_as_ram_main
movb $0x69, %ah
jmp .Lhlt
halt1:

27
src/soc/intel/quark/romstage/romstage.c Normal file
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@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <fsp/car.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
void car_soc_pre_console_init(void)
{
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
UART_BASE_ADDRESS);
}

42
src/soc/intel/quark/romstage/uart.c Normal file
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@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2006-2010 coresystems GmbH
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
#include <device/pci.h>
#include <device/pci_def.h>
#include <rules.h>
#include <soc/romstage.h>
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
{
uint16_t reg16;
/* HSUART controller #1 (B0:D20:F5). */
device_t uart_dev = PCI_DEV(bus, dev, func);
/* Decode BAR0(offset 0x10). */
pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable MEMBASE at CMD(offset 0x04). */
reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(uart_dev, PCI_COMMAND, reg16);
return 0;
}

36
src/soc/intel/quark/tsc_freq.c Normal file
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@ -0,0 +1,36 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
static unsigned long bus_freq_khz(void)
{
/* cpu freq = 400 MHz */
return 400 * 1000;
}
unsigned long tsc_freq_mhz(void)
{
/* assume ratio=1 */
unsigned bclk_khz = bus_freq_khz();
if (!bclk_khz)
return 0;
return (bclk_khz * 1) / 1000;
}

40
src/soc/intel/quark/uart.c Normal file
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@ -0,0 +1,40 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2006-2010 coresystems GmbH
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
#include <console/uart.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <rules.h>
#include <soc/pci_devs.h>
unsigned int uart_platform_refclk(void)
{
return 44236800;
}
uintptr_t uart_platform_base(int idx)
{
/* HSUART controller #1 (B0:D20:F5). */
device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
/* UART base address at BAR0(offset 0x10). */
return (unsigned int) (pci_read_config32(dev,
PCI_BASE_ADDRESS_0) & ~0xfff);
}