GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/util/autoport/sandybridge.go

148 lines
4.8 KiB
Go
Raw Normal View History

autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
package main
type sandybridgemc struct {
}
func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
inteltool := ctx.InfoSource.GetInteltool()
/* FIXME:XX Move this somewhere else. */
MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
MainboardEnable += (` /* FIXME: fix those values*/
util/autoport: Break very long line Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30968 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 01:12:21 +01:00
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
`)
pchLVDS := inteltool.IGD[0xe1180]
dualChannel := pchLVDS&(3<<2) == (3 << 2)
pipe := (pchLVDS >> 30) & 1
link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
link_factor := float32(link_m1) / float32(link_n1)
fp0 := inteltool.IGD[0xc6040+8*pipe]
dpll := inteltool.IGD[0xc6014+4*pipe]
pixel_m2 := fp0 & 0xff
pixel_m1 := (fp0>>8)&0xff + 2
pixel_p1 := uint32(1)
for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 {
pixel_p1++
}
pixel_n := ((fp0 >> 16) & 0xff) + 2
pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0)
if !dualChannel {
pixel_frequency /= 2
}
link_frequency := pixel_frequency / link_factor
DevTree = DevTreeNode{
Chip: "northbridge/intel/sandybridge",
MissingParent: "northbridge",
Comment: "FIXME: check gfx.ndid and gfx.did",
Registers: map[string]string{
"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
"gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
"gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
"gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
"gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
"gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
"gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
"gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
/* FIXME:XX hardcoded. */
"gfx.ndid": "3",
util/autoport: Trim gfx.did to size Since the values are hardcoded, we might as well hardcode values that make sense. Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 16:16:52 +01:00
"gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }",
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
},
Children: []DevTreeNode{
{
Chip: "cpu_cluster",
Dev: 0,
Children: []DevTreeNode{
{
Chip: "cpu/intel/model_206ax",
Comment: "FIXME: check all registers",
Registers: map[string]string{
/* FIXME:XX hardcoded. */
"c1_acpower": "1",
"c2_acpower": "3",
"c3_acpower": "5",
"c1_battery": "1",
"c2_battery": "3",
"c3_battery": "5",
},
Children: []DevTreeNode{
cpu/intel/model_206ax: Remove the notion of sockets With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-21 17:55:02 +01:00
{
Chip: "lapic",
Dev: 0,
},
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
{
Chip: "lapic",
Dev: 0xacac,
Disabled: true,
},
},
},
},
},
{
Chip: "domain",
Dev: 0,
PCIController: true,
ChildPCIBus: 0,
PCISlots: []PCISlot{
PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
},
},
},
}
PutPCIDev(addr, "Host bridge")
/* FIXME:XX some configs are unsupported. */
nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-10 16:48:14 +02:00
KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
Make MRC vs native a config rather than making a separate chipset for it. Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 02:36:04 +01:00
KconfigBool["USE_NATIVE_RAMINIT"] = true
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
KconfigBool["INTEL_INT15"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true
KconfigInt["MAX_CPUS"] = 8
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
util/autoport: Correct DSDT include statement With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file), some model_206ax code was moved to a common place. However, autoport was not updated accordingly. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30967 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 00:18:33 +01:00
File: "cpu/intel/common/acpi/cpu.asl",
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
})
DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
gma ACPI: Make brightness levels a per board setting Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-08-27 13:31:46 +02:00
}, DSDTInclude{
File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
})
}
func init() {
nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-10 16:48:14 +02:00
RegisterPCI(0x8086, 0x0100, sandybridgemc{})
RegisterPCI(0x8086, 0x0104, sandybridgemc{})
RegisterPCI(0x8086, 0x0150, sandybridgemc{})
RegisterPCI(0x8086, 0x0154, sandybridgemc{})
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
for _, id := range []uint16{
intel/sandybridge: Clean VGA BIOS ids up a little Sync map_oprom_vendev() and autoport with the list of PCI ids in the `gma.c` driver, remove one obsolete Kconfig default override. Change-Id: I12f24f415b695c516fbb947114e09c873af2e439 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-29 01:46:23 +02:00
0x0102, 0x0106, 0x010a,
0x0112, 0x0116, 0x0122, 0x0126,
0x0152, 0x0156, 0x0162, 0x0166,
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
} {
RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
}
util/autoport: Separate NB and SB PCIe port IDs The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10 19:52:51 +01:00
/* PCIe bridge */
for _, id := range []uint16{
0x0101, 0x0105, 0x0109, 0x010d,
0x0151, 0x0155, 0x0159, 0x015d,
} {
RegisterPCI(0x8086, id, GenericPCI{})
}
autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-10-15 21:51:47 +02:00
}