coreboot-kgpe-d16/src/southbridge/nvidia/mcp55/Kconfig

config SOUTHBRIDGE_NVIDIA_MCP55
	bool
	select IOAPIC
	select HAVE_USBDEBUG

config ID_SECTION_OFFSET
	hex
	default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55

config EHCI_BAR
	hex
	default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55

config EHCI_DEBUG_OFFSET
	hex
	default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
Add support for Nvidia Southbridges to Kconfig. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2009-08-24 20:36:02 +02:00			`config SOUTHBRIDGE_NVIDIA_MCP55`
			`bool`
Move all IOAPIC selection to southbridges, and remove them from mainboards. Some adaptations were necessary after the IOAPIC cleanup, so this should fix the build. Fix intel/d945gclf build, which was missing some ACPI component. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2010-01-18 18:30:36 +01:00			`select IOAPIC`
Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2010-09-26 09:35:55 +02:00			`select HAVE_USBDEBUG`
Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2009-11-27 17:55:13 +01:00
			`config ID_SECTION_OFFSET`
			`hex`
			`default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55`
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2010-10-05 15:40:31 +02:00
			`config EHCI_BAR`
			`hex`
			`default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55`

			`config EHCI_DEBUG_OFFSET`
			`hex`
			`default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55`