coreboot-kgpe-d16/src/include/device/pciexp.h

#ifndef DEVICE_PCIEXP_H
#define DEVICE_PCIEXP_H
/* (c) 2005 Linux Networx GPL see COPYING for details */

enum aspm_type {
	PCIE_ASPM_NONE = 0,
	PCIE_ASPM_L0S  = 1,
	PCIE_ASPM_L1   = 2,
	PCIE_ASPM_BOTH = 3,
};

unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
			     unsigned int max_devfn, unsigned int max);
unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);

extern struct device_operations default_pciexp_ops_bus;

#endif /* DEVICE_PCIEXP_H */
eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2005-07-08 04:49:49 +02:00			`#ifndef DEVICE_PCIEXP_H`
			`#define DEVICE_PCIEXP_H`
			`/* (c) 2005 Linux Networx GPL see COPYING for details */`

Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) 2011-10-25 23:15:11 +02:00			`enum aspm_type {`
			`PCIE_ASPM_NONE = 0,`
			`PCIE_ASPM_L0S = 1,`
			`PCIE_ASPM_L1 = 2,`
			`PCIE_ASPM_BOTH = 3,`
			`};`

Cosmetics and coding style fixes in devices/*. - Whitespace and indentation fixes in various places. - Fix various typos. - Use u8, u16 etc. everywhere. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2010-10-18 02:00:57 +02:00			`unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,`
			`unsigned int max_devfn, unsigned int max);`
eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2005-07-08 04:49:49 +02:00			`unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);`

			`extern struct device_operations default_pciexp_ops_bus;`

			`#endif /* DEVICE_PCIEXP_H */`