2013-11-25 11:20:20 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <edid.h>
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#include <stdlib.h>
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
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static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
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static u32 addr = 0;
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enum
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{
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VGA_CR_HTOTAL = 0x00,
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VGA_CR_HORIZ_END = 0x01,
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VGA_CR_HBLANK_START = 0x02,
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VGA_CR_HBLANK_END = 0x03,
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VGA_CR_HORIZ_SYNC_PULSE_START = 0x04,
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VGA_CR_HORIZ_SYNC_PULSE_END = 0x05,
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VGA_CR_VERT_TOTAL = 0x06,
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VGA_CR_OVERFLOW = 0x07,
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VGA_CR_BYTE_PANNING = 0x08,
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VGA_CR_CELL_HEIGHT = 0x09,
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VGA_CR_CURSOR_START = 0x0a,
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VGA_CR_CURSOR_END = 0x0b,
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VGA_CR_START_ADDR_HIGH_REGISTER = 0x0c,
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VGA_CR_START_ADDR_LOW_REGISTER = 0x0d,
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VGA_CR_CURSOR_ADDR_HIGH = 0x0e,
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VGA_CR_CURSOR_ADDR_LOW = 0x0f,
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VGA_CR_VSYNC_START = 0x10,
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VGA_CR_VSYNC_END = 0x11,
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VGA_CR_VDISPLAY_END = 0x12,
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VGA_CR_PITCH = 0x13,
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VGA_CR_UNDERLINE_LOCATION = 0x14,
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VGA_CR_VERTICAL_BLANK_START = 0x15,
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VGA_CR_VERTICAL_BLANK_END = 0x16,
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VGA_CR_MODE = 0x17,
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VGA_CR_LINE_COMPARE = 0x18,
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};
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#define VGA_IO_MISC_COLOR 0x01
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#define VGA_CR_WIDTH_DIVISOR 8
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#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT 7
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#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK 0x02
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#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT 3
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#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK 0x40
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#define VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT 8
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#define VGA_CR_OVERFLOW_VERT_TOTAL1_MASK 0x01
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#define VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT 4
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#define VGA_CR_OVERFLOW_VERT_TOTAL2_MASK 0x20
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#define VGA_CR_OVERFLOW_VSYNC_START1_SHIFT 6
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#define VGA_CR_OVERFLOW_VSYNC_START1_MASK 0x04
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#define VGA_CR_OVERFLOW_VSYNC_START2_SHIFT 2
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#define VGA_CR_OVERFLOW_VSYNC_START2_MASK 0x80
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#define VGA_CR_OVERFLOW_HEIGHT1_SHIFT 7
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#define VGA_CR_OVERFLOW_HEIGHT1_MASK 0x02
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#define VGA_CR_OVERFLOW_HEIGHT2_SHIFT 3
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#define VGA_CR_OVERFLOW_HEIGHT2_MASK 0xc0
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#define VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT 4
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#define VGA_CR_OVERFLOW_LINE_COMPARE_MASK 0x10
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#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK 0x40
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#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT 3
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#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK 0x20
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#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT 4
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#define VGA_CR_CELL_HEIGHT_DOUBLE_SCAN 0x80
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enum
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{
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VGA_CR_CURSOR_START_DISABLE = (1 << 5)
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};
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#define VGA_CR_PITCH_DIVISOR 8
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enum
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{
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VGA_CR_MODE_NO_CGA = 0x01,
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VGA_CR_MODE_NO_HERCULES = 0x02,
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VGA_CR_MODE_ADDRESS_WRAP = 0x20,
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VGA_CR_MODE_BYTE_MODE = 0x40,
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VGA_CR_MODE_TIMING_ENABLE = 0x80
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};
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enum
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{
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VGA_SR_RESET = 0,
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VGA_SR_CLOCKING_MODE = 1,
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VGA_SR_MAP_MASK_REGISTER = 2,
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VGA_SR_CHAR_MAP_SELECT = 3,
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VGA_SR_MEMORY_MODE = 4,
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};
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enum
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{
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VGA_SR_RESET_ASYNC = 1,
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VGA_SR_RESET_SYNC = 2
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};
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enum
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{
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VGA_SR_CLOCKING_MODE_8_DOT_CLOCK = 1
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};
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enum
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{
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VGA_SR_MEMORY_MODE_NORMAL = 0,
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VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY = 2,
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VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING = 4,
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VGA_SR_MEMORY_MODE_CHAIN4 = 8,
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};
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enum
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{
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VGA_GR_SET_RESET_PLANE = 0,
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VGA_GR_SET_RESET_PLANE_ENABLE = 1,
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VGA_GR_COLOR_COMPARE = 2,
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VGA_GR_READ_MAP_REGISTER = 4,
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VGA_GR_MODE = 5,
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VGA_GR_GR6 = 6,
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VGA_GR_COLOR_COMPARE_DISABLE = 7,
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VGA_GR_BITMASK = 8,
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VGA_GR_MAX
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};
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enum
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{
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VGA_TEXT_TEXT_PLANE = 0,
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VGA_TEXT_ATTR_PLANE = 1,
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VGA_TEXT_FONT_PLANE = 2
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};
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enum
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{
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VGA_GR_GR6_GRAPHICS_MODE = 1,
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VGA_GR_GR6_MMAP_A0 = (1 << 2),
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VGA_GR_GR6_MMAP_CGA = (3 << 2)
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};
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enum
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{
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VGA_GR_MODE_READ_MODE1 = 0x08,
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VGA_GR_MODE_ODD_EVEN = 0x10,
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VGA_GR_MODE_ODD_EVEN_SHIFT = 0x20,
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VGA_GR_MODE_256_COLOR = 0x40
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};
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#define CIRRUS_CR_EXTENDED_DISPLAY 0x1b
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#define CIRRUS_CR_EXTENDED_OVERLAY 0x1d
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#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK 0x10
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#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT 4
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#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1 0x1
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#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT1 16
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#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2 0xc
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#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT2 15
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#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK 0x80
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#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_SHIFT 12
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#define CIRRUS_SR_EXTENDED_MODE 7
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#define CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE 0xf0
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#define CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT 0x01
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#define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08
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#define CIRRUS_HIDDEN_DAC_888COLOR 0xc5
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static void
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write_hidden_dac (uint8_t data)
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{
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inb (0x3c8);
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inb (0x3c6);
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inb (0x3c6);
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inb (0x3c6);
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inb (0x3c6);
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outb (data, 0x3c6);
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}
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2017-05-20 16:46:01 +02:00
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static void cirrus_init_linear_fb(struct device *dev)
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2013-11-25 11:20:20 +01:00
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{
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uint8_t cr_ext, cr_overlay;
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unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR;
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uint8_t sr_ext = 0, hidden_dac = 0;
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unsigned vdisplay_end = height - 2;
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unsigned line_compare = 0x3ff;
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uint8_t overflow, cell_height_reg;
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unsigned horizontal_end = width / VGA_CR_WIDTH_DIVISOR;
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unsigned horizontal_total = horizontal_end + 40;
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unsigned horizontal_blank_start = horizontal_end;
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unsigned horizontal_sync_pulse_start = horizontal_end + 3;
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unsigned horizontal_sync_pulse_end = 0;
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unsigned horizontal_blank_end = 0;
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unsigned vertical_blank_start = height + 1;
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unsigned vertical_blank_end = 0;
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unsigned vertical_sync_start = height + 3;
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unsigned vertical_sync_end = 0;
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unsigned vertical_total = height + 40;
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/* find lfb pci bar */
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addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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addr &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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printk(BIOS_DEBUG, "QEMU VGA: cirrus framebuffer @ %x (pci bar 0)\n",
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addr);
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vga_misc_write (VGA_IO_MISC_COLOR);
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vga_sr_write (VGA_SR_MEMORY_MODE,
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VGA_SR_MEMORY_MODE_NORMAL);
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vga_sr_write (VGA_SR_MAP_MASK_REGISTER,
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(1 << VGA_TEXT_TEXT_PLANE)
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| (1 << VGA_TEXT_ATTR_PLANE));
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vga_sr_write (VGA_SR_CLOCKING_MODE,
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VGA_SR_CLOCKING_MODE_8_DOT_CLOCK);
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vga_palette_disable();
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/* Disable CR0-7 write protection. */
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vga_cr_write (VGA_CR_VSYNC_END, 0);
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overflow = ((vertical_total >> VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT)
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& VGA_CR_OVERFLOW_VERT_TOTAL1_MASK)
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| ((vertical_total >> VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT)
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& VGA_CR_OVERFLOW_VERT_TOTAL2_MASK)
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| ((vertical_sync_start >> VGA_CR_OVERFLOW_VSYNC_START2_SHIFT)
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& VGA_CR_OVERFLOW_VSYNC_START2_MASK)
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| ((vertical_sync_start >> VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
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& VGA_CR_OVERFLOW_VSYNC_START1_MASK)
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| ((vdisplay_end >> VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT)
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& VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK)
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| ((vdisplay_end >> VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT)
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& VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK)
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| ((vertical_sync_start >> VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
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& VGA_CR_OVERFLOW_VSYNC_START1_MASK)
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| ((line_compare >> VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT)
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& VGA_CR_OVERFLOW_LINE_COMPARE_MASK);
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cell_height_reg = ((vertical_blank_start
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>> VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT)
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& VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK)
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| ((line_compare >> VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT)
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& VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK);
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vga_cr_write (VGA_CR_HTOTAL, horizontal_total - 1);
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vga_cr_write (VGA_CR_HORIZ_END, horizontal_end - 1);
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vga_cr_write (VGA_CR_HBLANK_START, horizontal_blank_start - 1);
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vga_cr_write (VGA_CR_HBLANK_END, horizontal_blank_end);
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vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_START,
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horizontal_sync_pulse_start);
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vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_END,
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horizontal_sync_pulse_end);
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vga_cr_write (VGA_CR_VERT_TOTAL, vertical_total & 0xff);
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vga_cr_write (VGA_CR_OVERFLOW, overflow);
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vga_cr_write (VGA_CR_CELL_HEIGHT, cell_height_reg);
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vga_cr_write (VGA_CR_VSYNC_START, vertical_sync_start & 0xff);
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vga_cr_write (VGA_CR_VSYNC_END, vertical_sync_end & 0x0f);
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vga_cr_write (VGA_CR_VDISPLAY_END, vdisplay_end & 0xff);
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vga_cr_write (VGA_CR_PITCH, pitch & 0xff);
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vga_cr_write (VGA_CR_VERTICAL_BLANK_START, vertical_blank_start & 0xff);
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vga_cr_write (VGA_CR_VERTICAL_BLANK_END, vertical_blank_end & 0xff);
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vga_cr_write (VGA_CR_LINE_COMPARE, line_compare & 0xff);
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vga_gr_write (VGA_GR_MODE, VGA_GR_MODE_256_COLOR | VGA_GR_MODE_READ_MODE1);
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vga_gr_write (VGA_GR_GR6, VGA_GR_GR6_GRAPHICS_MODE);
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vga_sr_write (VGA_SR_MEMORY_MODE, VGA_SR_MEMORY_MODE_NORMAL);
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vga_cr_write (CIRRUS_CR_EXTENDED_DISPLAY,
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(pitch >> CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT)
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& CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK);
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vga_cr_write (VGA_CR_MODE, VGA_CR_MODE_TIMING_ENABLE
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| VGA_CR_MODE_BYTE_MODE
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| VGA_CR_MODE_NO_HERCULES | VGA_CR_MODE_NO_CGA);
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vga_cr_write (VGA_CR_START_ADDR_LOW_REGISTER, 0);
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vga_cr_write (VGA_CR_START_ADDR_HIGH_REGISTER, 0);
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cr_ext = vga_cr_read (CIRRUS_CR_EXTENDED_DISPLAY);
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cr_ext &= ~(CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1
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| CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2);
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vga_cr_write (CIRRUS_CR_EXTENDED_DISPLAY, cr_ext);
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cr_overlay = vga_cr_read (CIRRUS_CR_EXTENDED_OVERLAY);
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cr_overlay &= ~(CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK);
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vga_cr_write (CIRRUS_CR_EXTENDED_OVERLAY, cr_overlay);
|
|
|
|
|
|
|
|
sr_ext = CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE
|
|
|
|
| CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT
|
|
|
|
| CIRRUS_SR_EXTENDED_MODE_32BPP;
|
|
|
|
hidden_dac = CIRRUS_HIDDEN_DAC_888COLOR;
|
|
|
|
vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext);
|
|
|
|
write_hidden_dac (hidden_dac);
|
|
|
|
|
|
|
|
|
|
|
|
struct edid edid;
|
2015-09-04 12:58:00 +02:00
|
|
|
edid.mode.ha = width;
|
|
|
|
edid.mode.va = height;
|
2014-08-27 11:23:35 +02:00
|
|
|
edid.panel_bits_per_color = 8;
|
|
|
|
edid.panel_bits_per_pixel = 24;
|
2016-04-06 21:50:40 +02:00
|
|
|
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
|
2013-11-25 11:20:20 +01:00
|
|
|
set_vbe_mode_info_valid(&edid, addr);
|
2017-05-20 16:46:01 +02:00
|
|
|
}
|
2014-02-22 10:35:45 +01:00
|
|
|
|
2017-05-20 16:46:01 +02:00
|
|
|
static void cirrus_init_text_mode(struct device *dev)
|
|
|
|
{
|
|
|
|
vga_misc_write(0x1);
|
2014-02-22 10:35:45 +01:00
|
|
|
vga_textmode_init();
|
2017-05-20 16:46:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void cirrus_init(struct device *dev)
|
|
|
|
{
|
2019-03-06 01:53:33 +01:00
|
|
|
if (CONFIG(LINEAR_FRAMEBUFFER))
|
2017-05-20 16:46:01 +02:00
|
|
|
cirrus_init_linear_fb(dev);
|
2019-03-06 01:53:33 +01:00
|
|
|
else if (CONFIG(VGA_TEXT_FRAMEBUFFER))
|
2017-05-20 16:46:01 +02:00
|
|
|
cirrus_init_text_mode(dev);
|
2013-11-25 11:20:20 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct device_operations qemu_cirrus_graph_ops = {
|
|
|
|
.read_resources = pci_dev_read_resources,
|
|
|
|
.set_resources = pci_dev_set_resources,
|
|
|
|
.enable_resources = pci_dev_enable_resources,
|
|
|
|
.init = cirrus_init,
|
|
|
|
.scan_bus = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct pci_driver qemu_cirrus_driver __pci_driver = {
|
|
|
|
.ops = &qemu_cirrus_graph_ops,
|
|
|
|
.vendor = 0x1013,
|
|
|
|
.device = 0x00b8,
|
|
|
|
};
|