coreboot-kgpe-d16/src/soc/intel/cannonlake/Makefile.inc

ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)

subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc

bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c

romstage-y += cbmem.c
romstage-y += reset.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c

ramstage-y += cbmem.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c

CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake

CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include

endif
soc/intel/cannonlake: Add initial dummy directory Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-05-03 03:54:44 +02:00			`ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)`

soc/intel/cannonlake: Add Makefile This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-06-06 03:24:50 +02:00			`subdirs-y += ../../../cpu/x86/mtrr`
			`subdirs-y += ../../../cpu/x86/tsc`

			`bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c`
			`bootblock-y += bootblock/bootblock.c`
			`bootblock-y += bootblock/cpu.c`
			`bootblock-y += bootblock/pch.c`
			`bootblock-y += bootblock/report_platform.c`
			`bootblock-y += gpio.c`

soc/intel/cannonlake: Add initial dummy directory Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-05-03 03:54:44 +02:00			`romstage-y += cbmem.c`
soc/intel/cannonlake: Add Makefile This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-06-06 03:24:50 +02:00			`romstage-y += reset.c`
			`romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c`
soc/intel/cannonlake: Add initial dummy directory Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-05-03 03:54:44 +02:00
			`ramstage-y += cbmem.c`
soc/intel/cannonlake: Add Makefile This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-06-06 03:24:50 +02:00			`ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c`
			`ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c`

			`CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20`
			`CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake`

			`CPPFLAGS_common += -I$(src)/soc/intel/cannonlake`
			`CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include`
soc/intel/cannonlake: Add initial dummy directory Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-05-03 03:54:44 +02:00
			`endif`