93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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/* USB Phy Registers */
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#define USB2_GLOBAL_PORT 0x4001
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#define USB2_PLL1 0x7F02
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#define USB2_PLL2 0x7F03
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#define USB2_COMPBG 0x7F04
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/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
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* reference clock and Port2 as a USB device port, the following sequence must
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* be followed
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*/
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static const struct reg_script init_script[] = {
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/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
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* For port 0 & 1 as host and port 2 as device.
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*/
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REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
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/*
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* Sighting #4930653 Required BIOS change on Disconnect vref to change
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* to 600mV.
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*/
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REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
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(BIT10 | BIT7)),
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/* Sideband register write to USB AFE (Phy)
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* (pllbypass) to bypass/Disable PLL before switch
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*/
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REG_USB_OR(USB2_PLL2, BIT29),
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/* Sideband register write to USB AFE (Phy)
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* (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
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* (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
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*/
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REG_USB_OR(USB2_PLL1, BIT1),
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/* Sideband register write to USB AFE (Phy)
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* (divide by 8) to achieve internal 480MHz clock
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* for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
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*/
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REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
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/* Sideband register write to USB AFE (Phy)
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* Clear (pllbypass)
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*/
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REG_USB_AND(USB2_PLL2, ~BIT29),
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/* Sideband register write to USB AFE (Phy)
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* Set (startlock) to force the PLL FSM to restart the lock
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* sequence due to input clock/freq switch.
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*/
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REG_USB_OR(USB2_PLL2, BIT24),
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REG_SCRIPT_END
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};
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static void init(device_t dev)
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{
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printk(BIOS_INFO, "Initializing USB PLLs\n");
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reg_script_run_on_dev(dev, init_script);
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = init,
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};
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static const struct pci_driver driver __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = EHCI_DEVID,
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};
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