2013-01-03 02:41:51 +01:00
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config BOOTBLOCK_OFFSET
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hex "Bootblock offset"
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default 0x3400
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help
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This is where the Coreboot bootblock resides. For Exynos5250,
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this value is pre-determined by the vendor-provided BL1.
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2012-12-08 02:18:43 +01:00
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config EXYNOS_ACE_SHA
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bool
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default n
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config SATA_AHCI
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bool
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default n
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config SPL_BUILD
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bool
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default n
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config SYS_TEXT_BASE
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hex "Executable code section"
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default 0x43e00000
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x40000000
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#FIXME(dhendrix, reinauer): re-visit this RAMBASE/RAMTOP stuff...
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config RAMBASE
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hex
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default SYS_SDRAM_BASE
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# according to stefan, this is RAMBASE + 1M.
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config RAMTOP
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hex
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default 0x40100000
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2012-12-27 22:50:32 +01:00
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config IRAM_BOTTOM
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hex
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default 0x02020000
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config IRAM_TOP
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hex
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default 0x02077fff
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config SYS_INIT_SP_ADDR
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hex
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default 0x0204F800
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config IRAM_STACK
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hex
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default SYS_INIT_SP_ADDR
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config XIP_ROM_SIZE
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hex "ROM stage (BL2) size"
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default 0x20000
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