coreboot-kgpe-d16/src/northbridge/intel/e7520/raminit.h

#ifndef RAMINIT_H
#define RAMINIT_H

#define DIMM_SOCKETS 4
struct mem_controller {
	unsigned node_id;
	// device_t f0, f1, f2, f3;
	u16 channel0[DIMM_SOCKETS];
	u16 channel1[DIMM_SOCKETS];
};

#endif /* RAMINIT_H */
eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2005-07-08 04:49:49 +02:00			`#ifndef RAMINIT_H`
			`#define RAMINIT_H`

			`#define DIMM_SOCKETS 4`
			`struct mem_controller {`
			`unsigned node_id;`
This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2010-03-31 16:34:40 +02:00			`// device_t f0, f1, f2, f3;`
			`u16 channel0[DIMM_SOCKETS];`
			`u16 channel1[DIMM_SOCKETS];`
eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2005-07-08 04:49:49 +02:00			`};`

			`#endif /* RAMINIT_H */`