coreboot-kgpe-d16/src/lib/coreboot_table.c

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003-2004 Eric Biederman
* Copyright (C) 2005-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <console/uart.h>
#include <ip_checksum.h>
#include <boot/coreboot_tables.h>
#include <boot_device.h>
#include <string.h>
#include <version.h>
#include <boardid.h>
#include <device/device.h>
#include <fmap.h>
#include <stdlib.h>
#include <cbfs.h>
#include <cbmem.h>
#include <bootmem.h>
drivers/spi: Pass flash parameters from coreboot to payload A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-08 19:29:19 +01:00
#include <spi_flash.h>
#if CONFIG_USE_OPTION_TABLE
#include <option_table.h>
#endif
#if CONFIG_CHROMEOS
#if CONFIG_HAVE_ACPI_TABLES
#include <arch/acpi.h>
#endif
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
#if CONFIG_ARCH_X86
#include <cpu/x86/mtrr.h>
#endif
static struct lb_header *lb_table_init(unsigned long addr)
{
struct lb_header *header;
/* 16 byte align the address */
addr += 15;
addr &= ~15;
header = (void *)addr;
header->signature[0] = 'L';
header->signature[1] = 'B';
header->signature[2] = 'I';
header->signature[3] = 'O';
header->header_bytes = sizeof(*header);
header->header_checksum = 0;
header->table_bytes = 0;
header->table_checksum = 0;
header->table_entries = 0;
return header;
}
static struct lb_record *lb_first_record(struct lb_header *header)
{
struct lb_record *rec;
rec = (void *)(((char *)header) + sizeof(*header));
return rec;
}
static struct lb_record *lb_last_record(struct lb_header *header)
{
struct lb_record *rec;
rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes);
return rec;
}
arm: libpayload: Add cache coherent DMA memory definition and management This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 00:48:32 +02:00
struct lb_record *lb_new_record(struct lb_header *header)
{
struct lb_record *rec;
rec = lb_last_record(header);
if (header->table_entries) {
header->table_bytes += rec->size;
}
rec = lb_last_record(header);
header->table_entries++;
rec->tag = LB_TAG_UNUSED;
rec->size = sizeof(*rec);
return rec;
}
static struct lb_memory *lb_memory(struct lb_header *header)
{
struct lb_record *rec;
struct lb_memory *mem;
rec = lb_new_record(header);
mem = (struct lb_memory *)rec;
mem->tag = LB_TAG_MEMORY;
mem->size = sizeof(*mem);
return mem;
}
void lb_add_serial(struct lb_serial *new_serial, void *data)
{
struct lb_header *header = (struct lb_header *)data;
struct lb_serial *serial;
serial = (struct lb_serial *)lb_new_record(header);
serial->tag = LB_TAG_SERIAL;
serial->size = sizeof(*serial);
serial->type = new_serial->type;
serial->baseaddr = new_serial->baseaddr;
serial->baud = new_serial->baud;
serial->regwidth = new_serial->regwidth;
}
void lb_add_console(uint16_t consoletype, void *data)
{
struct lb_header *header = (struct lb_header *)data;
struct lb_console *console;
console = (struct lb_console *)lb_new_record(header);
console->tag = LB_TAG_CONSOLE;
console->size = sizeof(*console);
console->type = consoletype;
}
void __attribute__((weak)) lb_framebuffer(struct lb_header *header)
{
#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
oprom: Ensure that mode information is valid before putting it in the tables. At least when CONFIG_CHROMEOS is turned on, it's possible for CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid information to put into the framebuffer coreboot table. That means that what's put in there is junk, probably all zeroes from the uninitialized global variable the mode information is stored in (mode_info). When a payload uses libpayload and turns on the coreboot framebuffer console, that console will attempt to scroll at some point and decrease the cursor's y coordinate until it is less than the number of rows claimed by the console. The number of rows is computed by taking the vertical resolution of the framebuffer and dividing it by the height of the font. Because the mode information was all zeroes, the coreboot table info is all zeroes, and that means that the number of rows the console claims is zero. You can't get the unsigned y coordinate of the cursor to be less than zero, so libpayload gets stuck in an infinite loop. The solution this change implements is to add a new function, vbe_mode_info_valid, which simply returns whether or not mode_info has anything in it. If not, the framebuffer coreboot table is not created, and libpayload doesn't get stuck. Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-30 13:47:48 +02:00
int vbe_mode_info_valid(void);
oprom: Ensure that mode information is valid before putting it in the tables. At least when CONFIG_CHROMEOS is turned on, it's possible for CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid information to put into the framebuffer coreboot table. That means that what's put in there is junk, probably all zeroes from the uninitialized global variable the mode information is stored in (mode_info). When a payload uses libpayload and turns on the coreboot framebuffer console, that console will attempt to scroll at some point and decrease the cursor's y coordinate until it is less than the number of rows claimed by the console. The number of rows is computed by taking the vertical resolution of the framebuffer and dividing it by the height of the font. Because the mode information was all zeroes, the coreboot table info is all zeroes, and that means that the number of rows the console claims is zero. You can't get the unsigned y coordinate of the cursor to be less than zero, so libpayload gets stuck in an infinite loop. The solution this change implements is to add a new function, vbe_mode_info_valid, which simply returns whether or not mode_info has anything in it. If not, the framebuffer coreboot table is not created, and libpayload doesn't get stuck. Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-30 13:47:48 +02:00
// If there isn't any mode info to put in the table, don't ask for it
// to be filled with junk.
if (!vbe_mode_info_valid())
return;
struct lb_framebuffer *framebuffer;
framebuffer = (struct lb_framebuffer *)lb_new_record(header);
fill_lb_framebuffer(framebuffer);
framebuffer->tag = LB_TAG_FRAMEBUFFER;
framebuffer->size = sizeof(*framebuffer);
#endif
}
void fill_lb_gpio(struct lb_gpio *gpio, int num,
int polarity, const char *name, int value)
{
memset(gpio, 0, sizeof(*gpio));
gpio->port = num;
gpio->polarity = polarity;
if (value >= 0)
gpio->value = value;
strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
}
#if CONFIG_CHROMEOS
static void lb_gpios(struct lb_header *header)
{
struct lb_gpios *gpios;
gpios = (struct lb_gpios *)lb_new_record(header);
gpios->tag = LB_TAG_GPIO;
gpios->size = sizeof(*gpios);
gpios->count = 0;
fill_lb_gpios(gpios);
}
static void lb_vdat(struct lb_header *header)
{
#if CONFIG_HAVE_ACPI_TABLES
struct lb_range *vdat;
vdat = (struct lb_range *)lb_new_record(header);
vdat->tag = LB_TAG_VDAT;
vdat->size = sizeof(*vdat);
acpi_get_vdat_info(&vdat->range_start, &vdat->range_size);
#endif
}
static void lb_vbnv(struct lb_header *header)
{
#if CONFIG_PC80_SYSTEM
struct lb_range *vbnv;
vbnv = (struct lb_range *)lb_new_record(header);
vbnv->tag = LB_TAG_VBNV;
vbnv->size = sizeof(*vbnv);
vbnv->range_start = CONFIG_VBNV_OFFSET + 14;
vbnv->range_size = CONFIG_VBNV_SIZE;
#endif
}
#if CONFIG_VBOOT_VERIFY_FIRMWARE
static void lb_vboot_handoff(struct lb_header *header)
{
void *addr;
uint32_t size;
struct lb_range *vbho;
if (vboot_get_handoff_info(&addr, &size))
return;
vbho = (struct lb_range *)lb_new_record(header);
vbho->tag = LB_TAB_VBOOT_HANDOFF;
vbho->size = sizeof(*vbho);
vbho->range_start = (intptr_t)addr;
vbho->range_size = size;
}
#else
static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
#endif /* CONFIG_CHROMEOS */
static void lb_board_id(struct lb_header *header)
{
#if CONFIG_BOARD_ID_AUTO || CONFIG_BOARD_ID_MANUAL
struct lb_board_id *bid;
bid = (struct lb_board_id *)lb_new_record(header);
bid->tag = LB_TAG_BOARD_ID;
bid->size = sizeof(*bid);
bid->board_id = board_id();
#endif
}
static void lb_boot_media_params(struct lb_header *header)
{
struct lb_boot_media_params *bmp;
struct cbfs_props props;
const struct region_device *boot_dev;
struct region_device fmrd;
boot_device_init();
if (cbfs_boot_region_properties(&props))
return;
boot_dev = boot_device_ro();
if (boot_dev == NULL)
return;
bmp = (struct lb_boot_media_params *)lb_new_record(header);
bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS;
bmp->size = sizeof(*bmp);
bmp->cbfs_offset = props.offset;
bmp->cbfs_size = props.size;
bmp->boot_media_size = region_device_sz(boot_dev);
bmp->fmap_offset = ~(uint64_t)0;
if (find_fmap_directory(&fmrd) == 0) {
bmp->fmap_offset = region_device_offset(&fmrd);
}
}
static void lb_ram_code(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT)
struct lb_ram_code *code;
code = (struct lb_ram_code *)lb_new_record(header);
code->tag = LB_TAG_RAM_CODE;
code->size = sizeof(*code);
code->ram_code = ram_code();
#endif
}
static void add_cbmem_pointers(struct lb_header *header)
{
/*
* These CBMEM sections' addresses are included in the coreboot table
* with the appropriate tags.
*/
const struct section_id {
int cbmem_id;
int table_tag;
} section_ids[] = {
{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE},
{CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS},
{CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}
};
int i;
for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
const struct section_id *sid = section_ids + i;
struct lb_cbmem_ref *cbmem_ref;
void *cbmem_addr = cbmem_find(sid->cbmem_id);
if (!cbmem_addr)
continue; /* This section is not present */
cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
if (!cbmem_ref) {
printk(BIOS_ERR, "No more room in coreboot table!\n");
break;
}
cbmem_ref->tag = sid->table_tag;
cbmem_ref->size = sizeof(*cbmem_ref);
cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr;
}
}
static struct lb_mainboard *lb_mainboard(struct lb_header *header)
{
struct lb_record *rec;
struct lb_mainboard *mainboard;
rec = lb_new_record(header);
mainboard = (struct lb_mainboard *)rec;
mainboard->tag = LB_TAG_MAINBOARD;
mainboard->size = (sizeof(*mainboard) +
strlen(mainboard_vendor) + 1 +
strlen(mainboard_part_number) + 1 +
3) & ~3;
mainboard->vendor_idx = 0;
mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
memcpy(mainboard->strings + mainboard->vendor_idx,
mainboard_vendor, strlen(mainboard_vendor) + 1);
memcpy(mainboard->strings + mainboard->part_number_idx,
mainboard_part_number, strlen(mainboard_part_number) + 1);
return mainboard;
}
#if CONFIG_USE_OPTION_TABLE
static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
{
struct lb_record *rec;
struct cmos_checksum *cmos_checksum;
rec = lb_new_record(header);
cmos_checksum = (struct cmos_checksum *)rec;
cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
cmos_checksum->size = (sizeof(*cmos_checksum));
cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
cmos_checksum->location = LB_CKS_LOC * 8;
cmos_checksum->type = CHECKSUM_PCBIOS;
return cmos_checksum;
}
#endif
static void lb_strings(struct lb_header *header)
{
static const struct {
uint32_t tag;
const char *string;
} strings[] = {
{ LB_TAG_VERSION, coreboot_version, },
{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
{ LB_TAG_BUILD, coreboot_build, },
{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
};
unsigned int i;
for(i = 0; i < ARRAY_SIZE(strings); i++) {
struct lb_string *rec;
size_t len;
rec = (struct lb_string *)lb_new_record(header);
len = strlen(strings[i].string);
rec->tag = strings[i].tag;
rec->size = (sizeof(*rec) + len + 1 + 3) & ~3;
memcpy(rec->string, strings[i].string, len+1);
}
}
static void lb_record_version_timestamp(struct lb_header *header)
{
struct lb_timestamp *rec;
rec = (struct lb_timestamp *)lb_new_record(header);
rec->tag = LB_TAG_VERSION_TIMESTAMP;
rec->size = sizeof(*rec);
rec->timestamp = coreboot_version_timestamp;
}
arm: libpayload: Add cache coherent DMA memory definition and management This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 00:48:32 +02:00
void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;
struct lb_forward *forward;
rec = lb_new_record(header);
forward = (struct lb_forward *)rec;
forward->tag = LB_TAG_FORWARD;
forward->size = sizeof(*forward);
forward->forward = (uint64_t)(unsigned long)next_header;
return forward;
}
static unsigned long lb_table_fini(struct lb_header *head)
{
struct lb_record *rec, *first_rec;
rec = lb_last_record(head);
if (head->table_entries) {
head->table_bytes += rec->size;
}
first_rec = lb_first_record(head);
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
printk(BIOS_DEBUG,
"Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
head, head->table_bytes, head->table_checksum);
return (unsigned long)rec + rec->size;
}
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
struct lb_header *head;
if (low_table_start || low_table_end) {
printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
low_table_end);
head = lb_table_init(low_table_end);
lb_forward(head, (struct lb_header*)rom_table_end);
low_table_end = (unsigned long) lb_table_fini(head);
printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n",
low_table_end);
low_table_end = ALIGN(low_table_end, 4096);
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end);
}
printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n",
rom_table_end);
head = lb_table_init(rom_table_end);
rom_table_end = (unsigned long)head;
printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
rom_table_end = ALIGN(rom_table_end, (64 * 1024));
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
#if CONFIG_USE_OPTION_TABLE
{
struct cmos_option_table *option_table =
cbfs_boot_map_with_leak("cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
if (option_table) {
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
memcpy(rec_dest, option_table, option_table->size);
/* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
}
}
#endif
/* Initialize the memory map at boot time. */
bootmem_init();
if (low_table_start || low_table_end) {
uint64_t size = low_table_end - low_table_start;
/* Record the mptable and the the lb_table.
* (This will be adjusted later) */
bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
}
cbmem: dynamic cbmem support This patch adds a parallel implementation of cbmem that supports dynamic sizing. The original implementation relied on reserving a fixed-size block of memory for adding cbmem entries. In order to allow for more flexibility for adding cbmem allocations the dynamic cbmem infrastructure was developed as an alternative to the fixed block approach. Also, the amount of memory to reserve for cbmem allocations does not need to be known prior to the first allocation. The dynamic cbmem code implements the same API as the existing cbmem code except for cbmem_init() and cbmem_reinit(). The add and find routines behave the same way. The dynamic cbmem infrastructure uses a top down allocator that starts allocating from a board/chipset defined function cbmem_top(). A root pointer lives just below cbmem_top(). In turn that pointer points to the root block which contains the entries for all the large alloctations. The corresponding block for each large allocation falls just below the previous entry. It should be noted that this implementation rounds all allocations up to a 4096 byte granularity. Though a packing allocator could be written for small allocations it was deemed OK to just fragment the memory as there shouldn't be that many small allocations. The result is less code with a tradeoff of some wasted memory. +----------------------+ <- cbmem_top() | +----| root pointer | | | +----------------------+ | | | |--------+ | +--->| root block |-----+ | | +----------------------+ | | | | | | | | | | | | | | alloc N |<----+ | | +----------------------+ | | | | | | | | | \|/ | alloc N + 1 |<-------+ v +----------------------+ In addition to preserving the previous cbmem API, the dynamic cbmem API allows for removing blocks from cbmem. This allows for the boot process to allocate memory that can be discarded after it's been used for performing more complex boot tasks in romstage. In order to plumb this support in there were some issues to work around regarding writing of coreboot tables. There were a few assumptions to how cbmem was layed out which dictated some ifdef guarding and other runtime checks so as not to incorrectly tag the e820 and coreboot memory tables. The example shown below is using dynamic cbmem infrastructure. The reserved memory for cbmem is less than 512KiB. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000002ffff: RAM 2. 0000000000030000-000000000003ffff: RESERVED 3. 0000000000040000-000000000009ffff: RAM 4. 00000000000a0000-00000000000fffff: RESERVED 5. 0000000000100000-0000000000efffff: RAM 6. 0000000000f00000-0000000000ffffff: RESERVED 7. 0000000001000000-000000007bf80fff: RAM 8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES 9. 000000007c000000-000000007e9fffff: RESERVED 10. 00000000f0000000-00000000f3ffffff: RESERVED 11. 00000000fed10000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-00000001005fffff: RAM Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf coreboot table: 948 bytes. CBMEM ROOT 0. 7bfff000 00001000 MRC DATA 1. 7bffe000 00001000 ROMSTAGE 2. 7bffd000 00001000 TIME STAMP 3. 7bffc000 00001000 ROMSTG STCK 4. 7bff7000 00005000 CONSOLE 5. 7bfe7000 00010000 VBOOT 6. 7bfe6000 00001000 RAMSTAGE 7. 7bf98000 0004e000 GDT 8. 7bf97000 00001000 ACPI 9. 7bf8b000 0000c000 ACPI GNVS 10. 7bf8a000 00001000 SMBIOS 11. 7bf89000 00001000 COREBOOT 12. 7bf81000 00008000 And the corresponding e820 entries: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16 BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2848 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 18:41:44 +01:00
/* Record the pirq table, acpi tables, and maybe the mptable. However,
* these only need to be added when the rom_table is sitting below
* 1MiB. If it isn't that means high tables are being written.
* The code below handles high tables correctly. */
if (rom_table_end <= (1 << 20)) {
uint64_t size = rom_table_end - rom_table_start;
bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
}
/* No other memory areas can be added after the memory table has been
* committed as the entries won't show up in the serialize mem table. */
bootmem_write_memory_table(lb_memory(head));
/* Record our motherboard */
lb_mainboard(head);
/* Record the serial ports and consoles */
#if CONFIG_CONSOLE_SERIAL
uart_fill_lb(head);
#endif
#if CONFIG_CONSOLE_USB
lb_add_console(LB_TAG_CONSOLE_EHCI, head);
#endif
/* Record our various random string information */
lb_strings(head);
lb_record_version_timestamp(head);
/* Record our framebuffer */
lb_framebuffer(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
/* pass along the VDAT buffer address */
lb_vdat(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
/* Add board ID if available */
lb_board_id(head);
/* Add RAM config if available */
lb_ram_code(head);
drivers/spi: Pass flash parameters from coreboot to payload A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-08 19:29:19 +01:00
#if IS_ENABLED(CONFIG_SPI_FLASH)
/* Add SPI flash description if available */
lb_spi_flash(head);
#endif
add_cbmem_pointers(head);
arm: libpayload: Add cache coherent DMA memory definition and management This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 00:48:32 +02:00
/* Add board-specific table entries, if any. */
lb_board(head);
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
lb_ramoops(head);
#endif
lb_boot_media_params(head);
/* Remember where my valid memory ranges are */
return lb_table_fini(head);
}