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coreboot-kgpe-d16/src/soc/intel/skylake/bootblock/timestamp.inc

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soc/intel: Update license headers Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-10 19:09:16 +02:00
/*
* This file is part of the coreboot project.
*
soc/intel: Unify `timestamp.inc` These files are actually indentical, but unfortunately, the formatting was changed without caring for the already present files. Fix that. Use the license formatting where less lines are used. The next step is to put that in a common location. Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19423 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-22 09:35:18 +02:00
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
soc/intel: Update license headers Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-10 19:09:16 +02:00
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
/*
* Store the initial timestamp for booting in mmx registers. This works
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
* because the bootblock isn't being compiled with MMX support so mm0 and
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
* mm1 will be preserved into romstage.
*/
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.code32
.global stash_timestamp
stash_timestamp:
/* Save the BIST value */
movl %eax, %ebp
finit
rdtsc
movd %eax, %mm0
movd %edx, %mm1
/* Restore the BIST value to %eax */
movl %ebp, %eax
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