2013-03-15 03:06:11 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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2013-03-25 23:02:29 +01:00
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* cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
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*
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* Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
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2013-03-15 03:06:11 +01:00
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*/
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2013-03-29 21:24:29 +01:00
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#include <stdint.h>
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2013-03-15 03:06:11 +01:00
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#include <arch/cache.h>
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#define bitmask(high, low) ((1UL << (high)) + \
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((1UL << (high)) - 1) - ((1UL << (low)) - 1))
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/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */
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/* FIXME: src/include/lib.h is difficult to work with due to romcc */
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static unsigned long log2(unsigned long u)
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{
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int i = 0;
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while (u >>= 1)
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i++;
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return i;
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}
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void tlb_invalidate_all(void)
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{
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/*
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* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
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2013-03-25 23:02:29 +01:00
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* instruction vs. data TLBs is deprecated in ARMv7, however this does
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* not seem to be the case as of Cortex-A15.
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2013-03-15 03:06:11 +01:00
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*/
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tlbiall();
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dtlbiall();
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itlbiall();
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isb();
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dsb();
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}
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void icache_invalidate_all(void)
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{
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2013-03-25 23:02:29 +01:00
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/*
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* icache can be entirely invalidated with one operation.
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2013-03-15 03:06:11 +01:00
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* Note: If branch predictors are architecturally-visible, ICIALLU
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* also performs a BPIALL operation (B2-1283 in arch manual)
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*/
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iciallu();
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isb();
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}
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enum dcache_op {
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OP_DCCISW,
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2013-03-25 23:02:29 +01:00
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OP_DCISW,
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OP_DCCIMVAC,
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OP_DCCMVAC,
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2013-07-08 06:27:13 +02:00
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OP_DCIMVAC,
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2013-03-15 03:06:11 +01:00
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};
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2013-03-25 23:02:29 +01:00
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/*
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* Do a dcache operation on entire cache by set/way. This is done for
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* portability because mapping of memory address to cache location is
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* implementation defined (See note on "Requirements for operations by
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* set/way" in arch ref. manual).
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*/
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2013-03-15 03:06:11 +01:00
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static void dcache_op_set_way(enum dcache_op op)
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{
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uint32_t ccsidr;
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unsigned int associativity, num_sets, linesize_bytes;
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unsigned int set, way;
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unsigned int level;
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level = (read_csselr() >> 1) & 0x7;
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/*
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* dcache must be invalidated by set/way for portability since virtual
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* memory mapping is system-defined. The number of sets and
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* associativity is given by CCSIDR. We'll use DCISW to invalidate the
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* dcache.
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*/
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ccsidr = read_ccsidr();
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/* FIXME: rounding up required here? */
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num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1;
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associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1;
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/* FIXME: do we need to use CTR.DminLine here? */
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linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
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2013-03-25 23:02:29 +01:00
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dsb();
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2013-03-15 03:06:11 +01:00
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/*
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* Set/way operations require an interesting bit packing. See section
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* B4-35 in the ARMv7 Architecture Reference Manual:
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*
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* A: Log2(associativity)
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* B: L+S
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* L: Log2(linesize)
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* S: Log2(num_sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < associativity; way++) {
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for (set = 0; set < num_sets; set++) {
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uint32_t val = 0;
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val |= way << (32 - log2(associativity));
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val |= set << log2(linesize_bytes);
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val |= level << 1;
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switch(op) {
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case OP_DCCISW:
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dccisw(val);
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break;
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case OP_DCISW:
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dcisw(val);
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break;
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default:
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break;
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}
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}
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}
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2013-03-25 23:02:29 +01:00
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isb();
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2013-03-15 03:06:11 +01:00
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}
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2013-03-29 21:24:29 +01:00
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static void dcache_foreach(enum dcache_op op)
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{
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uint32_t clidr;
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int level;
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clidr = read_clidr();
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for (level = 0; level < 7; level++) {
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unsigned int ctype = (clidr >> (level * 3)) & 0x7;
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uint32_t csselr;
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switch(ctype) {
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case 0x2:
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case 0x3:
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case 0x4:
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csselr = level << 1;
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write_csselr(csselr);
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dcache_op_set_way(op);
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break;
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default:
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/* no cache, icache only, or reserved */
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break;
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}
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}
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}
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2013-03-15 03:06:11 +01:00
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void dcache_clean_invalidate_all(void)
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{
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2013-03-29 21:24:29 +01:00
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dcache_foreach(OP_DCCISW);
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2013-03-15 03:06:11 +01:00
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}
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void dcache_invalidate_all(void)
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{
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2013-03-29 21:24:29 +01:00
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dcache_foreach(OP_DCISW);
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2013-03-15 03:06:11 +01:00
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}
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static unsigned int line_bytes(void)
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{
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uint32_t ccsidr;
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unsigned int size;
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ccsidr = read_ccsidr();
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/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
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size = 1 << ((ccsidr & 0x7) + 2); /* words per line */
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size *= sizeof(unsigned int); /* bytes per line */
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return size;
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}
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2013-03-25 23:02:29 +01:00
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/*
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* Do a dcache operation by modified virtual address. This is useful for
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* maintaining coherency in drivers which do DMA transfers and only need to
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* perform cache maintenance on a particular memory range rather than the
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* entire cache.
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*/
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static void dcache_op_mva(unsigned long addr,
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unsigned long len, enum dcache_op op)
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{
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unsigned long line, linesize;
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linesize = line_bytes();
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line = addr & ~(linesize - 1);
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dsb();
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while (line < addr + len) {
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switch(op) {
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case OP_DCCIMVAC:
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dccimvac(line);
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break;
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2013-07-08 06:25:34 +02:00
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case OP_DCCMVAC:
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dccmvac(line);
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break;
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2013-07-08 06:27:13 +02:00
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case OP_DCIMVAC:
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dcimvac(line);
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break;
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2013-03-25 23:02:29 +01:00
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default:
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break;
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}
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line += linesize;
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}
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isb();
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}
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void dcache_clean_by_mva(unsigned long addr, unsigned long len)
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{
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dcache_op_mva(addr, len, OP_DCCMVAC);
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}
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2013-03-15 03:06:11 +01:00
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void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
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{
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2013-03-25 23:02:29 +01:00
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dcache_op_mva(addr, len, OP_DCCIMVAC);
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}
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2013-07-08 06:27:13 +02:00
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void dcache_invalidate_by_mva(unsigned long addr, unsigned long len)
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{
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dcache_op_mva(addr, len, OP_DCIMVAC);
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}
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2013-03-25 23:02:29 +01:00
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void dcache_mmu_disable(void)
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{
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2013-03-29 21:24:29 +01:00
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uint32_t sctlr;
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2013-03-25 23:02:29 +01:00
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dcache_clean_invalidate_all();
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sctlr = read_sctlr();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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write_sctlr(sctlr);
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}
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void dcache_mmu_enable(void)
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{
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uint32_t sctlr;
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2013-03-15 03:06:11 +01:00
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2013-03-25 23:02:29 +01:00
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sctlr = read_sctlr();
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dcache_clean_invalidate_all();
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sctlr |= SCTLR_C | SCTLR_M;
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write_sctlr(sctlr);
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2013-03-15 03:06:11 +01:00
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}
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2013-03-25 23:02:29 +01:00
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void armv7_invalidate_caches(void)
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2013-03-15 03:06:11 +01:00
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{
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2013-03-25 23:02:29 +01:00
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uint32_t clidr;
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int level;
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/* Invalidate branch predictor */
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bpiall();
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/* Iterate thru each cache identified in CLIDR and invalidate */
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clidr = read_clidr();
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for (level = 0; level < 7; level++) {
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unsigned int ctype = (clidr >> (level * 3)) & 0x7;
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uint32_t csselr;
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switch(ctype) {
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case 0x0:
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/* no cache */
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break;
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case 0x1:
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/* icache only */
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csselr = (level << 1) | 1;
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write_csselr(csselr);
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icache_invalidate_all();
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break;
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case 0x2:
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case 0x4:
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/* dcache only or unified cache */
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2013-03-29 21:24:29 +01:00
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csselr = level << 1;
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write_csselr(csselr);
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2013-03-25 23:02:29 +01:00
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dcache_invalidate_all();
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break;
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case 0x3:
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/* separate icache and dcache */
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csselr = (level << 1) | 1;
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write_csselr(csselr);
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icache_invalidate_all();
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2013-03-29 21:24:29 +01:00
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csselr = level << 1;
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2013-03-25 23:02:29 +01:00
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write_csselr(csselr);
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dcache_invalidate_all();
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break;
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default:
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/* reserved */
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break;
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}
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}
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/* Invalidate TLB */
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tlb_invalidate_all();
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2013-03-15 03:06:11 +01:00
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}
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