50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA124_FLOW_H_
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#define _TEGRA124_FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events; /* offset 0x00 */
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u32 halt_cop_events; /* offset 0x04 */
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u32 cpu_csr; /* offset 0x08 */
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u32 cop_csr; /* offset 0x0c */
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u32 xrq_events; /* offset 0x10 */
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u32 halt_cpu1_events; /* offset 0x14 */
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u32 cpu1_csr; /* offset 0x18 */
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u32 halt_cpu2_events; /* offset 0x1c */
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u32 cpu2_csr; /* offset 0x20 */
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u32 halt_cpu3_events; /* offset 0x24 */
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u32 cpu3_csr; /* offset 0x28 */
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u32 cluster_control; /* offset 0x2c */
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u32 halt_cop1_events; /* offset 0x30 */
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u32 halt_cop1_csr; /* offset 0x34 */
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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#define EVENT_MSEC (1 << 24)
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#define EVENT_USEC (1 << 25)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
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#define ACTIVE_LP (1 << 0)
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#endif /* _TEGRA124_FLOW_H_ */
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