2016-05-10 22:09:44 +02:00
|
|
|
/*
|
|
|
|
* This file is part of the coreboot project.
|
|
|
|
*
|
|
|
|
* Copyright 2016 Google Inc.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; version 2 of the License.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
DefinitionBlock(
|
|
|
|
"dsdt.aml",
|
|
|
|
"DSDT",
|
|
|
|
0x05, // DSDT revision: ACPI v5.0
|
|
|
|
"COREv4", // OEM id
|
|
|
|
"COREBOOT", // OEM table id
|
|
|
|
0x20110725 // OEM revision
|
|
|
|
)
|
|
|
|
{
|
|
|
|
/* global NVS and variables */
|
2016-06-14 07:29:00 +02:00
|
|
|
#include <soc/intel/apollolake/acpi/globalnvs.asl>
|
2016-05-10 22:09:44 +02:00
|
|
|
|
2016-06-04 02:11:12 +02:00
|
|
|
/* CPU */
|
|
|
|
#include <soc/intel/apollolake/acpi/cpu.asl>
|
|
|
|
|
2016-05-10 22:09:44 +02:00
|
|
|
Scope (\_SB) {
|
|
|
|
Device (PCI0)
|
|
|
|
{
|
|
|
|
#include <soc/intel/apollolake/acpi/northbridge.asl>
|
|
|
|
#include <soc/intel/apollolake/acpi/southbridge.asl>
|
2016-06-27 03:25:34 +02:00
|
|
|
#include <soc/intel/apollolake/acpi/pch_hda.asl>
|
2016-05-10 22:09:44 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Chrome OS specific */
|
|
|
|
#include "acpi/chromeos.asl"
|
|
|
|
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
|
|
|
|
|
|
|
/* Chipset specific sleep states */
|
|
|
|
#include <soc/intel/apollolake/acpi/sleepstates.asl>
|
|
|
|
|
|
|
|
/* Mainboard Specific devices */
|
|
|
|
#include "acpi/mainboard.asl"
|
|
|
|
}
|