GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/southbridge/intel/common/pmbase.c

106 lines
2.1 KiB
C
Raw Normal View History

sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic - should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-26 11:58:14 +02:00
#include <arch/acpi.h>
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
#include <arch/io.h>
security/vboot: relocate and rename vboot_platform_is_resuming() After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-24 16:08:35 +01:00
#include <bootmode.h>
device/pci: Fix PCI accessor headers PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01 12:43:02 +01:00
#include <device/pci_ops.h>
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
#include <device/device.h>
#include <device/pci.h>
#include <assert.h>
#include "pmbase.h"
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic - should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-26 11:58:14 +02:00
#include "pmutil.h"
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
/* LPC PM Base Address Register */
#define PMBASE 0x40
#define PMSIZE 0x80
/* PCI Configuration Space (D31:F0): LPC */
#if defined(__SIMPLE_DEVICE__)
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
#else
device: Use pcidev_on_root() Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-22 01:18:00 +02:00
#define PCH_LPC_DEV pcidev_on_root(0x1f, 0)
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
#endif
u16 lpc_get_pmbase(void)
{
arch/x86: Replace some __SMM__ guards We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 17:50:38 +01:00
#ifdef __SIMPLE_DEVICE__
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
/* Don't assume PMBASE is still the same */
return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
#else
sb/intel/common: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30506 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29 13:35:26 +01:00
static u16 pmbase;
sb/intel/common: Add functions to manipulate PMBASE Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:58:36 +02:00
if (pmbase)
return pmbase;
pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
return pmbase;
#endif
}
void write_pmbase32(const u8 addr, const u32 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u32)));
outl(val, lpc_get_pmbase() + addr);
}
void write_pmbase16(const u8 addr, const u16 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u16)));
outw(val, lpc_get_pmbase() + addr);
}
void write_pmbase8(const u8 addr, const u8 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u8)));
outb(val, lpc_get_pmbase() + addr);
}
u32 read_pmbase32(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u32)));
return inl(lpc_get_pmbase() + addr);
}
u16 read_pmbase16(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u16)));
return inw(lpc_get_pmbase() + addr);
}
u8 read_pmbase8(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u8)));
return inb(lpc_get_pmbase() + addr);
}
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic - should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-26 11:58:14 +02:00
security/vboot: relocate and rename vboot_platform_is_resuming() After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-24 16:08:35 +01:00
int platform_is_resuming(void)
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic - should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-26 11:58:14 +02:00
{
u16 reg16 = read_pmbase16(PM1_STS);
if (!(reg16 & WAK_STS))
return 0;
return acpi_sleep_from_pm1(reg16) == ACPI_S3;
}
Reference in a new issue Copy permalink