GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/Documentation/Intel/Board/board.html

240 lines
7.0 KiB
HTML
Raw Normal View History

Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<!DOCTYPE html>
<html>
<head>
<title>Board</title>
</head>
<body>
<h1>x86 Board Development</h1>
<p>
Board development requires System-on-a-Chip (SoC) support.
The combined steps are listed
Documentation: Fix links to Intel/documentation.html Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03 16:28:22 +01:00
<a target="_blank" href="../development.html">here</a>.
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
The development steps for the board are listed below:
</p>
<ol>
<li><a href="#RequiredFiles">Required Files</a></li>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<li><a href="#AcpiTables">ACPI Tables</a></li>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
</ol>
<hr>
Documentation/Intel: Adjust heading levels Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-15 20:33:50 +02:00
<h2><a name="RequiredFiles">Required Files</a></h2>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<p>
Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
</p>
<p>
The following files are required to build a new board:
</p>
<ol>
<li>Kconfig.name - Defines the Kconfig value for the board</li>
<li>Kconfig
<ol type="A">
<li>Selects the SoC for the board and specifies the SPI flash size
<ol type="I">
<li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
<li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
</ol>
</li>
<li>Declare the Kconfig values for:
<ol type="I">
<li>MAINBOARD_DIR</li>
<li>MAINBOARD_PART_NUMBER</li>
<li>MAINBOARD_VENDOR</li>
</ol>
</li>
</ol>
</li>
<li>devicetree.cb - Enable root bridge and serial port
<ol type="A">
<li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
this path is used by the generated static.c to include the chip.h
header file
</li>
</ol>
</li>
<li>romstage.c
<ol type="A">
<li>Add routine mainboard_romstage_entry which calls romstage_common</li>
</ol>
</li>
<li>Configure coreboot build:
<ol type="A">
<li>Set LOCALVERSION</li>
<li>Select vendor for the board</li>
<li>Select the board</li>
<li>CBFS_SIZE = 0x00100000</li>
<li>Set the CPU_MICROCODE_CBFS_LEN</li>
<li>Set the CPU_MICROCODE_CBFS_LOC</li>
<li>Set the FSP_IMAGE_ID_STRING</li>
<li>Set the FSP_LOC</li>
<li>No payload</li>
<li>Choose the default value for all other options</li>
</ol>
</li>
</ol>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<hr>
Documentation/Intel: Adjust heading levels Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-15 20:33:50 +02:00
<h2><a name="SerialOutput">Enable Serial Output</a></h2>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
<p>
Use the following steps to enable serial output:
</p>
<ol>
<li>Implement the car_mainboard_pre_console_init routine in the com_init.c
file:
<ol type="A">
<li>Power on and enable the UART controller</li>
<li>Connect the UART receive and transmit data lines to the
appropriate SoC pins
</li>
</ol>
</li>
<li>Add Makefile.inc
<ol type="A">
<li>Add com_init.c to romstage</li>
</ol>
</li>
</ol>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<hr>
Documentation/Intel: Adjust heading levels Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-15 20:33:50 +02:00
<h2><a name="SpdData">Memory Timing Data</a></h2>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
<p>
Memory timing data is located in the flash. This data is in the format of
<a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
(SPD) data.
Use the following steps to load the SPD data:
</p>
<ol>
<li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
display of the SPD data being passed to MemoryInit
</li>
<li>Create an "spd" subdirectory</li>
<li>Create an spd/spd.c file for the SPD implementation
<ol type="A">
<li>Implement the mainboard_fill_spd_data routine
<ol type="i">
<li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
<li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
<li>Set the DIMM channel configuration</li>
</ol>
</li>
</ol>
</li>
<li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
<li>Create spd/Makefile.inc
<ol type="A">
<li>Add spd.c to romstage</li>
<li>Add the .spd.hex file to SPD_SOURCES</li>
</ol>
</li>
<li>Edit Makefile.inc to add the spd subdirectory</li>
<li>Edit romstage.c
<ol type="A">
<li>Call mainboard_fill_spd_data</li>
<li>Add mainboard_memory_init_params to copy the SPD and DRAM
configuration data from the pei_data structure into the UPDs
for MemoryInit
</li>
</ol>
</li>
<li>Edit devicetree.cb
<ol type="A">
<li>Include the UPD parameters for MemoryInit except for:
<ul>
<li>Address of SPD data</li>
<li>DRAM configuration set above</li>
</ul>
</li>
</ol>
</li>
<li>A working FSP
<a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
routine is required to complete debugging</li>
<li>Debug the result until port 0x80 outputs
<ol type="A">
<li>0x34:
- Just after entering
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
</li>
<li>0x36:
- Just before displaying the
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
for FSP MemoryInit
</li>
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
- Just before calling FSP
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
</li>
<li>0x37:
- Just after returning from FSP
Use more secure HTTPS URLs for coreboot sites The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05 12:33:23 +02:00
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:23:36 +01:00
</li>
</ol>
</li>
<li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
</ol>
Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 20:21:33 +01:00
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<hr>
Documentation/Intel: Adjust heading levels Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-15 20:33:50 +02:00
<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
Documentation: x86 device tree processing and memory map Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14 23:55:29 +01:00
<p>
Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
of the devices in the system. Edit the devicetree.cb file:
</p>
<ol>
<li>Edit the devicetree.cb file:
<ol type="A">
<li>Add an entry for a PCI device.function and turn it off. The entry
should look similar to:
<pre><code>device pci 14.0 off end</code></pre>
</li>
<li>Turn on the devices for:
<ul>
<li>Memory Controller</li>
<li>Debug serial device</li>
</ul>
</li>
</ol>
</li>
<li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
</ol>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<hr>
Documentation/Intel: Adjust heading levels Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-15 20:33:50 +02:00
<h2><a name="AcpiTables">ACPI Tables</a></h2>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<ol>
<li>Edit Kconfig
<ol type="A">
<li>Add "select HAVE_ACPI_TABLES"</li>
</ol>
</li>
<li>Add the acpi_tables.c module:
<ol type="A">
<li>Include soc/acpi.h</li>
<li>Add the acpi_create_fadt routine
<ol type="I">
<li>fill in the ACPI header</li>
mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt() Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-30 17:02:32 +02:00
<li>Call the acpi_fill_fadt routine</li>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
</ol>
</li>
</ol>
</li>
<li>Add the dsdt.asl module:
</li>
</ol>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
<hr>
Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-21 02:48:35 +01:00
<p>Modified: 20 February 2016</p>
Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 20:24:24 +01:00
</body>
lib: remove FLASHMAP_OFFSET config variable The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-10 22:12:08 +02:00
</html>