2007-02-28 12:17:02 +01:00
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/*
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2009-07-21 23:20:45 +02:00
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* This file is part of the coreboot project.
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*
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2007-02-28 12:17:02 +01:00
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* Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com)
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2011-01-28 09:05:54 +01:00
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* Copyright (C) 2007 AMD
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2007-02-28 12:17:02 +01:00
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*
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2009-07-21 23:20:45 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2007-02-28 12:17:02 +01:00
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*
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2009-07-21 23:20:45 +02:00
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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2010-09-23 20:16:46 +02:00
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2011-01-28 09:05:54 +01:00
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#include <stddef.h>
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2007-02-28 12:17:02 +01:00
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#include <console/console.h>
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#include <arch/io.h>
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2013-07-09 03:19:22 +02:00
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#include <device/pci.h>
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2011-01-28 09:05:54 +01:00
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#include <arch/byteorder.h>
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2013-07-06 10:41:09 +02:00
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#include <cpu/x86/car.h>
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2013-07-28 22:16:47 +02:00
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#include <string.h>
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2007-02-28 12:17:02 +01:00
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#include <usb_ch9.h>
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#include <ehci.h>
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2010-05-25 18:17:45 +02:00
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#include <usbdebug.h>
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2007-02-28 12:17:02 +01:00
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2013-07-08 17:11:44 +02:00
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#define DBGP_EP_VALID (1<<0)
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#define DBGP_EP_ENABLED (1<<1)
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#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED)
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struct dbgp_pipe
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{
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u8 endpoint;
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u8 status;
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u8 bufidx;
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char buf[8];
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};
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#define DBGP_MAX_ENDPOINTS 4
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#define DBGP_CONSOLE_EPOUT 0
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#define DBGP_CONSOLE_EPIN 1
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struct ehci_debug_info {
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u8 devnum;
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void *ehci_caps;
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void *ehci_regs;
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void *ehci_debug;
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struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS];
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};
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2013-06-06 09:46:37 +02:00
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#if CONFIG_DEBUG_USBDEBUG
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2013-08-12 15:11:34 +02:00
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# define dprintk(LEVEL, args...) printk(LEVEL, args)
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2011-01-28 09:05:54 +01:00
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#else
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2013-08-12 15:11:34 +02:00
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# define dprintk(LEVEL, args...) do {} while(0)
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2011-01-28 09:05:54 +01:00
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#endif
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2007-02-28 12:17:02 +01:00
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#define USB_DEBUG_DEVNUM 127
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#define DBGP_DATA_TOGGLE 0x8800
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#define DBGP_PID_UPDATE(x, tok) \
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((((x) ^ DBGP_DATA_TOGGLE) & 0xffff00) | ((tok) & 0xff))
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#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
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/*
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* USB Packet IDs (PIDs)
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*/
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/* token */
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#define USB_PID_OUT 0xe1
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#define USB_PID_IN 0x69
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#define USB_PID_SOF 0xa5
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#define USB_PID_SETUP 0x2d
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/* handshake */
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#define USB_PID_ACK 0xd2
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#define USB_PID_NAK 0x5a
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#define USB_PID_STALL 0x1e
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#define USB_PID_NYET 0x96
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/* data */
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#define USB_PID_DATA0 0xc3
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#define USB_PID_DATA1 0x4b
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#define USB_PID_DATA2 0x87
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#define USB_PID_MDATA 0x0f
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/* Special */
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#define USB_PID_PREAMBLE 0x3c
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#define USB_PID_ERR 0x3c
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#define USB_PID_SPLIT 0x78
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#define USB_PID_PING 0xb4
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#define USB_PID_UNDEF_0 0xf0
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#define USB_PID_DATA_TOGGLE 0x88
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#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
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#define PCI_CAP_ID_EHCI_DEBUG 0xa
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#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
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#define HUB_SHORT_RESET_TIME 10
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#define HUB_LONG_RESET_TIME 200
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#define HUB_RESET_TIMEOUT 500
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#define DBGP_MAX_PACKET 8
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2012-07-25 14:19:45 +02:00
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#define DBGP_LOOPS 1000
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2007-02-28 12:17:02 +01:00
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2013-07-06 10:41:09 +02:00
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static struct ehci_debug_info glob_dbg_info CAR_GLOBAL;
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2013-07-06 10:56:49 +02:00
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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2013-07-09 03:19:22 +02:00
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static struct device_operations *ehci_drv_ops;
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static struct device_operations ehci_dbg_ops;
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2013-07-06 10:56:49 +02:00
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#endif
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2013-07-11 06:49:46 +02:00
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static inline struct ehci_debug_info *dbgp_ehci_info(void)
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{
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return car_get_var_ptr(&glob_dbg_info);
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}
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2007-02-28 12:17:02 +01:00
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static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
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{
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2011-01-28 09:05:54 +01:00
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u32 ctrl;
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2007-02-28 12:17:02 +01:00
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int loop = 0x100000;
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2011-01-28 09:05:54 +01:00
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2007-02-28 12:17:02 +01:00
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do {
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2010-05-25 18:35:51 +02:00
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ctrl = read32((unsigned long)&ehci_debug->control);
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2007-02-28 12:17:02 +01:00
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/* Stop when the transaction is finished */
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if (ctrl & DBGP_DONE)
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break;
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2011-01-28 09:05:54 +01:00
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} while (--loop > 0);
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2007-02-28 12:17:02 +01:00
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2011-01-28 09:05:54 +01:00
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if (!loop)
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return -1;
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2007-02-28 12:17:02 +01:00
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/* Now that we have observed the completed transaction,
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* clear the done bit.
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*/
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2010-05-25 18:35:51 +02:00
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write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
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2007-02-28 12:17:02 +01:00
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return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
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}
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static void dbgp_breath(void)
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{
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/* Sleep to give the debug port a chance to breathe */
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}
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2012-07-25 14:19:45 +02:00
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static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl, int loop)
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2007-02-28 12:17:02 +01:00
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{
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2011-01-28 09:05:54 +01:00
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u32 pids, lpid;
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2007-02-28 12:17:02 +01:00
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int ret;
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2011-01-28 09:05:54 +01:00
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2007-02-28 12:17:02 +01:00
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retry:
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2010-05-25 18:35:51 +02:00
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write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
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2007-02-28 12:17:02 +01:00
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ret = dbgp_wait_until_complete(ehci_debug);
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2010-05-25 18:35:51 +02:00
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pids = read32((unsigned long)&ehci_debug->pids);
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2007-02-28 12:17:02 +01:00
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lpid = DBGP_PID_GET(pids);
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2012-07-25 14:19:45 +02:00
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if (ret < 0) {
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if (ret == -DBGP_ERR_BAD && --loop > 0)
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goto retry;
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2007-02-28 12:17:02 +01:00
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return ret;
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2012-07-25 14:19:45 +02:00
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}
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2007-02-28 12:17:02 +01:00
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/* If the port is getting full or it has dropped data
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* start pacing ourselves, not necessary but it's friendly.
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*/
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if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
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dbgp_breath();
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2010-04-27 08:56:47 +02:00
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2007-02-28 12:17:02 +01:00
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/* If I get a NACK reissue the transmission */
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if (lpid == USB_PID_NAK) {
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2011-01-28 09:05:54 +01:00
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if (--loop > 0)
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goto retry;
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2007-02-28 12:17:02 +01:00
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}
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return ret;
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}
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static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
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{
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const unsigned char *bytes = buf;
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2011-01-28 09:05:54 +01:00
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u32 lo, hi;
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2007-02-28 12:17:02 +01:00
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int i;
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2011-01-28 09:05:54 +01:00
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2007-02-28 12:17:02 +01:00
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lo = hi = 0;
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for (i = 0; i < 4 && i < size; i++)
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lo |= bytes[i] << (8*i);
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for (; i < 8 && i < size; i++)
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hi |= bytes[i] << (8*(i - 4));
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2010-05-25 18:35:51 +02:00
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write32((unsigned long)&ehci_debug->data03, lo);
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write32((unsigned long)&ehci_debug->data47, hi);
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2007-02-28 12:17:02 +01:00
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}
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static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
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{
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unsigned char *bytes = buf;
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2011-01-28 09:05:54 +01:00
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u32 lo, hi;
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2007-02-28 12:17:02 +01:00
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int i;
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2011-01-28 09:05:54 +01:00
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2010-05-25 18:35:51 +02:00
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lo = read32((unsigned long)&ehci_debug->data03);
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hi = read32((unsigned long)&ehci_debug->data47);
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2007-02-28 12:17:02 +01:00
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for (i = 0; i < 4 && i < size; i++)
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bytes[i] = (lo >> (8*i)) & 0xff;
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for (; i < 8 && i < size; i++)
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bytes[i] = (hi >> (8*(i - 4))) & 0xff;
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}
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2011-10-31 20:56:45 +01:00
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static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug,
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2011-01-28 09:05:54 +01:00
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unsigned devnum, unsigned endpoint, const char *bytes, int size)
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2007-02-28 12:17:02 +01:00
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{
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2011-01-28 09:05:54 +01:00
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u32 pids, addr, ctrl;
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2007-02-28 12:17:02 +01:00
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int ret;
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2011-01-28 09:05:54 +01:00
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2007-02-28 12:17:02 +01:00
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if (size > DBGP_MAX_PACKET)
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return -1;
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addr = DBGP_EPADDR(devnum, endpoint);
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2010-05-25 18:35:51 +02:00
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pids = read32((unsigned long)&ehci_debug->pids);
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2007-02-28 12:17:02 +01:00
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pids = DBGP_PID_UPDATE(pids, USB_PID_OUT);
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2010-04-27 08:56:47 +02:00
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2010-05-25 18:35:51 +02:00
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ctrl = read32((unsigned long)&ehci_debug->control);
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2007-02-28 12:17:02 +01:00
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ctrl = DBGP_LEN_UPDATE(ctrl, size);
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ctrl |= DBGP_OUT;
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ctrl |= DBGP_GO;
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dbgp_set_data(ehci_debug, bytes, size);
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2010-05-25 18:35:51 +02:00
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write32((unsigned long)&ehci_debug->address, addr);
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write32((unsigned long)&ehci_debug->pids, pids);
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2007-02-28 12:17:02 +01:00
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2012-07-25 14:19:45 +02:00
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ret = dbgp_wait_until_done(ehci_debug, ctrl, DBGP_LOOPS);
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2011-01-28 09:05:54 +01:00
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2007-02-28 12:17:02 +01:00
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return ret;
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}
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|
2013-07-08 17:11:44 +02:00
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int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size)
|
2007-02-28 12:17:02 +01:00
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{
|
2013-07-08 17:11:44 +02:00
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struct ehci_debug_info *dbg_info = dbgp_ehci_info();
|
2011-01-28 09:05:54 +01:00
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return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum,
|
2013-07-08 17:11:44 +02:00
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pipe->endpoint, bytes, size);
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2007-02-28 12:17:02 +01:00
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}
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2011-01-28 09:05:54 +01:00
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static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum,
|
2012-07-25 14:19:45 +02:00
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unsigned endpoint, void *data, int size, int loops)
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2007-02-28 12:17:02 +01:00
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{
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2011-01-28 09:05:54 +01:00
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u32 pids, addr, ctrl;
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2007-02-28 12:17:02 +01:00
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int ret;
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if (size > DBGP_MAX_PACKET)
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return -1;
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addr = DBGP_EPADDR(devnum, endpoint);
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|
2010-05-25 18:35:51 +02:00
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pids = read32((unsigned long)&ehci_debug->pids);
|
2007-02-28 12:17:02 +01:00
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pids = DBGP_PID_UPDATE(pids, USB_PID_IN);
|
2010-04-27 08:56:47 +02:00
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2010-05-25 18:35:51 +02:00
|
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ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
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ctrl = DBGP_LEN_UPDATE(ctrl, size);
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ctrl &= ~DBGP_OUT;
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ctrl |= DBGP_GO;
|
2010-04-27 08:56:47 +02:00
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|
2010-05-25 18:35:51 +02:00
|
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write32((unsigned long)&ehci_debug->address, addr);
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write32((unsigned long)&ehci_debug->pids, pids);
|
2012-07-25 14:19:45 +02:00
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ret = dbgp_wait_until_done(ehci_debug, ctrl, loops);
|
2007-02-28 12:17:02 +01:00
|
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if (ret < 0)
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return ret;
|
2011-01-28 09:05:54 +01:00
|
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2007-02-28 12:17:02 +01:00
|
|
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if (size > ret)
|
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|
|
size = ret;
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|
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dbgp_get_data(ehci_debug, data, size);
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|
return ret;
|
|
|
|
}
|
2011-01-28 09:05:54 +01:00
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size)
|
2007-02-28 12:17:02 +01:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
|
2011-10-31 20:56:45 +01:00
|
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|
return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum,
|
2013-07-08 17:11:44 +02:00
|
|
|
pipe->endpoint, data, size, DBGP_LOOPS);
|
2011-01-28 09:05:54 +01:00
|
|
|
}
|
|
|
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|
|
static void dbgp_mdelay(int ms)
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|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
while (ms--) {
|
|
|
|
for (i = 0; i < 1000; i++)
|
|
|
|
inb(0x80);
|
|
|
|
}
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype,
|
|
|
|
int request, int value, int index, void *data, int size)
|
2007-02-28 12:17:02 +01:00
|
|
|
{
|
2011-01-28 09:05:54 +01:00
|
|
|
u32 pids, addr, ctrl;
|
2007-02-28 12:17:02 +01:00
|
|
|
struct usb_ctrlrequest req;
|
|
|
|
int read;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
read = (requesttype & USB_DIR_IN) != 0;
|
2011-01-28 09:05:54 +01:00
|
|
|
if (size > (read ? DBGP_MAX_PACKET:0))
|
2007-02-28 12:17:02 +01:00
|
|
|
return -1;
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2007-02-28 12:17:02 +01:00
|
|
|
/* Compute the control message */
|
|
|
|
req.bRequestType = requesttype;
|
|
|
|
req.bRequest = request;
|
2011-01-28 09:05:54 +01:00
|
|
|
req.wValue = cpu_to_le16(value);
|
|
|
|
req.wIndex = cpu_to_le16(index);
|
|
|
|
req.wLength = cpu_to_le16(size);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
|
|
|
|
addr = DBGP_EPADDR(devnum, 0);
|
|
|
|
|
2010-05-25 18:35:51 +02:00
|
|
|
ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
|
|
|
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
|
|
|
|
ctrl |= DBGP_OUT;
|
|
|
|
ctrl |= DBGP_GO;
|
|
|
|
|
|
|
|
/* Send the setup message */
|
|
|
|
dbgp_set_data(ehci_debug, &req, sizeof(req));
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_debug->address, addr);
|
|
|
|
write32((unsigned long)&ehci_debug->pids, pids);
|
2012-07-25 14:19:45 +02:00
|
|
|
ret = dbgp_wait_until_done(ehci_debug, ctrl, DBGP_LOOPS);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
|
|
/* Read the result */
|
2012-07-25 14:19:45 +02:00
|
|
|
ret = dbgp_bulk_read(ehci_debug, devnum, 0, data, size, DBGP_LOOPS);
|
2007-02-28 12:17:02 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
|
|
|
|
{
|
2011-01-28 09:05:54 +01:00
|
|
|
u32 portsc;
|
|
|
|
u32 delay_time, delay_ms;
|
2007-02-28 12:17:02 +01:00
|
|
|
int loop;
|
|
|
|
|
|
|
|
/* Reset the usb debug port */
|
2010-05-25 18:35:51 +02:00
|
|
|
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
2007-02-28 12:17:02 +01:00
|
|
|
portsc &= ~PORT_PE;
|
|
|
|
portsc |= PORT_RESET;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
2010-09-23 01:42:32 +02:00
|
|
|
delay_ms = HUB_ROOT_RESET_TIME;
|
2007-02-28 12:17:02 +01:00
|
|
|
for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
|
2010-09-23 01:42:32 +02:00
|
|
|
delay_time += delay_ms) {
|
|
|
|
dbgp_mdelay(delay_ms);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
2010-05-25 18:35:51 +02:00
|
|
|
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (portsc & PORT_RESET) {
|
|
|
|
/* force reset to complete */
|
|
|
|
loop = 2;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->port_status[port - 1],
|
2010-01-16 18:53:38 +01:00
|
|
|
portsc & ~(PORT_RWC_BITS | PORT_RESET));
|
2010-04-27 08:56:47 +02:00
|
|
|
do {
|
2010-09-23 01:42:32 +02:00
|
|
|
dbgp_mdelay(delay_ms);
|
2010-05-25 18:35:51 +02:00
|
|
|
portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
|
2010-09-23 01:42:32 +02:00
|
|
|
delay_time += delay_ms;
|
2007-02-28 12:17:02 +01:00
|
|
|
} while ((portsc & PORT_RESET) && (--loop > 0));
|
|
|
|
if (!loop) {
|
2010-03-22 12:42:32 +01:00
|
|
|
printk(BIOS_DEBUG, "ehci_reset_port forced done");
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Device went away? */
|
|
|
|
if (!(portsc & PORT_CONNECT))
|
2011-01-28 09:05:54 +01:00
|
|
|
return -1; //-ENOTCONN;
|
2007-02-28 12:17:02 +01:00
|
|
|
|
2013-07-10 05:51:14 +02:00
|
|
|
/* bomb out completely if something weird happened */
|
2007-02-28 12:17:02 +01:00
|
|
|
if ((portsc & PORT_CSC))
|
2011-01-28 09:05:54 +01:00
|
|
|
return -2; //-EINVAL;
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* If we've finished resetting, then break out of the loop */
|
|
|
|
if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
|
|
|
|
return 0;
|
|
|
|
}
|
2011-01-28 09:05:54 +01:00
|
|
|
return -3; //-EBUSY;
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
|
2007-02-28 12:17:02 +01:00
|
|
|
{
|
2011-01-28 09:05:54 +01:00
|
|
|
u32 status;
|
2007-02-28 12:17:02 +01:00
|
|
|
int ret, reps;
|
2011-01-28 09:05:54 +01:00
|
|
|
|
2007-02-28 12:17:02 +01:00
|
|
|
for (reps = 0; reps < 3; reps++) {
|
|
|
|
dbgp_mdelay(100);
|
2010-05-25 18:35:51 +02:00
|
|
|
status = read32((unsigned long)&ehci_regs->status);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (status & STS_PCD) {
|
|
|
|
ret = ehci_reset_port(ehci_regs, port);
|
|
|
|
if (ret == 0)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2011-01-28 09:05:54 +01:00
|
|
|
return -1; //-ENOTCONN;
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2013-07-06 10:56:49 +02:00
|
|
|
static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
|
2007-02-28 12:17:02 +01:00
|
|
|
{
|
|
|
|
struct ehci_caps *ehci_caps;
|
|
|
|
struct ehci_regs *ehci_regs;
|
|
|
|
struct ehci_dbg_port *ehci_debug;
|
2011-01-28 09:05:54 +01:00
|
|
|
|
2007-02-28 12:17:02 +01:00
|
|
|
struct usb_debug_descriptor dbgp_desc;
|
2011-01-28 09:05:54 +01:00
|
|
|
u32 cmd, ctrl, status, portsc, hcs_params;
|
|
|
|
u32 debug_port, new_debug_port = 0, n_ports;
|
|
|
|
u32 devnum;
|
|
|
|
int ret, i;
|
2007-02-28 12:17:02 +01:00
|
|
|
int loop;
|
2011-01-28 09:05:54 +01:00
|
|
|
int port_map_tried;
|
|
|
|
int playtimes = 3;
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
ehci_caps = (struct ehci_caps *)ehci_bar;
|
2011-10-31 20:56:45 +01:00
|
|
|
ehci_regs = (struct ehci_regs *)(ehci_bar +
|
2011-01-28 09:05:54 +01:00
|
|
|
HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
|
2007-02-28 12:17:02 +01:00
|
|
|
ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
|
|
|
|
info->ehci_debug = (void *)0;
|
2013-07-08 17:11:44 +02:00
|
|
|
|
|
|
|
memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
|
2007-02-28 12:17:02 +01:00
|
|
|
try_next_time:
|
|
|
|
port_map_tried = 0;
|
|
|
|
|
|
|
|
try_next_port:
|
2010-05-25 18:35:51 +02:00
|
|
|
hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
|
2007-02-28 12:17:02 +01:00
|
|
|
debug_port = HCS_DEBUG_PORT(hcs_params);
|
|
|
|
n_ports = HCS_N_PORTS(hcs_params);
|
|
|
|
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
|
|
|
|
dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
|
|
|
|
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
for (i = 1; i <= n_ports; i++) {
|
2010-05-25 18:35:51 +02:00
|
|
|
portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
if(port_map_tried && (new_debug_port != debug_port)) {
|
2007-02-28 12:17:02 +01:00
|
|
|
if(--playtimes) {
|
|
|
|
set_debug_port(debug_port);
|
|
|
|
goto try_next_time;
|
|
|
|
}
|
2011-01-28 09:05:54 +01:00
|
|
|
return -1;
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
loop = 100;
|
2007-02-28 12:17:02 +01:00
|
|
|
/* Reset the EHCI controller */
|
2010-05-25 18:35:51 +02:00
|
|
|
cmd = read32((unsigned long)&ehci_regs->command);
|
2007-02-28 12:17:02 +01:00
|
|
|
cmd |= CMD_RESET;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->command, cmd);
|
2007-02-28 12:17:02 +01:00
|
|
|
do {
|
2011-01-28 09:05:54 +01:00
|
|
|
dbgp_mdelay(10);
|
2010-05-25 18:35:51 +02:00
|
|
|
cmd = read32((unsigned long)&ehci_regs->command);
|
2007-02-28 12:17:02 +01:00
|
|
|
} while ((cmd & CMD_RESET) && (--loop > 0));
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
if(!loop) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
// on some systems it works without succeeding here.
|
|
|
|
// return -2;
|
|
|
|
} else {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI controller reset successfully.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
}
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Claim ownership, but do not enable yet */
|
2010-05-25 18:35:51 +02:00
|
|
|
ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
|
|
|
ctrl |= DBGP_OWNER;
|
|
|
|
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_debug->control, ctrl);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
/* Start EHCI controller */
|
2010-05-25 18:35:51 +02:00
|
|
|
cmd = read32((unsigned long)&ehci_regs->command);
|
2007-02-28 12:17:02 +01:00
|
|
|
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
|
|
|
|
cmd |= CMD_RUN;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->command, cmd);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Ensure everything is routed to the EHCI */
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Wait until the controller is no longer halted */
|
|
|
|
loop = 10;
|
|
|
|
do {
|
2011-01-28 09:05:54 +01:00
|
|
|
dbgp_mdelay(10);
|
2010-05-25 18:35:51 +02:00
|
|
|
status = read32((unsigned long)&ehci_regs->status);
|
2011-01-28 09:05:54 +01:00
|
|
|
} while ((status & STS_HALT) && (--loop > 0));
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
if(!loop) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI could not be started.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
return -3;
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI started.\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Wait for a device to show up in the debug port */
|
|
|
|
ret = ehci_wait_for_port(ehci_regs, debug_port);
|
|
|
|
if (ret < 0) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "No device found in debug port %d\n", debug_port);
|
2007-02-28 12:17:02 +01:00
|
|
|
goto next_debug_port;
|
|
|
|
}
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI done waiting for port.\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Enable the debug port */
|
2010-05-25 18:35:51 +02:00
|
|
|
ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
|
|
|
ctrl |= DBGP_CLAIM;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_debug->control, ctrl);
|
|
|
|
ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
|
|
|
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -4;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI debug port enabled.\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
/* Completely transfer the debug device to the debug controller */
|
2010-05-25 18:35:51 +02:00
|
|
|
portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
|
2007-02-28 12:17:02 +01:00
|
|
|
portsc &= ~PORT_PE;
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
dbgp_mdelay(100);
|
|
|
|
|
|
|
|
/* Find the debug device and make it device number 127 */
|
|
|
|
for (devnum = 0; devnum <= 127; devnum++) {
|
|
|
|
ret = dbgp_control_msg(ehci_debug, devnum,
|
|
|
|
USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
|
|
|
USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
|
|
|
|
&dbgp_desc, sizeof(dbgp_desc));
|
|
|
|
if (ret > 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (devnum > 127) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Could not find attached debug device.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -5;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
if (ret < 0) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Attached device is not a debug device.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -6;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Move the device to 127 if it isn't already there */
|
|
|
|
if (devnum != USB_DEBUG_DEVNUM) {
|
|
|
|
ret = dbgp_control_msg(ehci_debug, devnum,
|
|
|
|
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
2011-01-28 09:05:54 +01:00
|
|
|
USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (ret < 0) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
|
2007-02-28 12:17:02 +01:00
|
|
|
USB_DEBUG_DEVNUM);
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -7;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
devnum = USB_DEBUG_DEVNUM;
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable the debug interface */
|
|
|
|
ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
|
|
|
|
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
2011-01-28 09:05:54 +01:00
|
|
|
USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (ret < 0) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -8;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
/* Perform a small write to get the even/odd data state in sync */
|
2013-07-08 17:11:44 +02:00
|
|
|
ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_desc.bDebugOutEndpoint, "USB\r\n",5);
|
2007-02-28 12:17:02 +01:00
|
|
|
if (ret < 0) {
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
|
2011-01-28 09:05:54 +01:00
|
|
|
ret = -9;
|
2007-02-28 12:17:02 +01:00
|
|
|
goto err;
|
|
|
|
}
|
2013-08-12 15:11:34 +02:00
|
|
|
dprintk(BIOS_INFO, "Test write done\n");
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
info->ehci_caps = ehci_caps;
|
|
|
|
info->ehci_regs = ehci_regs;
|
|
|
|
info->ehci_debug = ehci_debug;
|
|
|
|
info->devnum = devnum;
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
|
|
|
|
info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
|
|
|
|
info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
|
|
|
|
info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
|
2011-01-28 09:05:54 +01:00
|
|
|
return 0;
|
2007-02-28 12:17:02 +01:00
|
|
|
err:
|
|
|
|
/* Things didn't work so remove my claim */
|
2010-05-25 18:35:51 +02:00
|
|
|
ctrl = read32((unsigned long)&ehci_debug->control);
|
2007-02-28 12:17:02 +01:00
|
|
|
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
|
2010-05-25 18:35:51 +02:00
|
|
|
write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
|
2011-01-28 09:05:54 +01:00
|
|
|
//return ret;
|
2007-02-28 12:17:02 +01:00
|
|
|
|
|
|
|
next_debug_port:
|
2011-01-28 09:05:54 +01:00
|
|
|
port_map_tried |= (1 << (debug_port - 1));
|
|
|
|
new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
|
|
|
|
if (port_map_tried != ((1 << n_ports) - 1)) {
|
2007-02-28 12:17:02 +01:00
|
|
|
set_debug_port(new_debug_port);
|
|
|
|
goto try_next_port;
|
|
|
|
}
|
2011-01-28 09:05:54 +01:00
|
|
|
if (--playtimes) {
|
|
|
|
//set_debug_port(new_debug_port);
|
2007-02-28 12:17:02 +01:00
|
|
|
set_debug_port(debug_port);
|
|
|
|
goto try_next_time;
|
|
|
|
}
|
|
|
|
|
2011-01-28 09:05:54 +01:00
|
|
|
return -10;
|
2007-02-28 12:17:02 +01:00
|
|
|
}
|
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data)
|
2011-01-28 09:05:54 +01:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
if (dbgp_ep_is_active(pipe)) {
|
|
|
|
pipe->buf[pipe->bufidx++] = data;
|
|
|
|
if (pipe->bufidx >= 8) {
|
|
|
|
dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
|
|
|
|
pipe->bufidx = 0;
|
2012-07-26 14:31:40 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
void usbdebug_tx_flush(struct dbgp_pipe *pipe)
|
2012-07-26 14:31:40 +02:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
if (dbgp_ep_is_active(pipe) && pipe->bufidx > 0) {
|
|
|
|
dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
|
|
|
|
pipe->bufidx = 0;
|
2011-01-28 09:05:54 +01:00
|
|
|
}
|
2013-07-05 20:38:54 +02:00
|
|
|
}
|
|
|
|
|
2013-07-09 03:19:22 +02:00
|
|
|
#if !defined(__PRE_RAM__) && !defined(__SMM__)
|
|
|
|
static void usbdebug_re_enable(unsigned ehci_base)
|
|
|
|
{
|
2013-07-11 06:49:46 +02:00
|
|
|
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
|
2013-07-09 03:19:22 +02:00
|
|
|
unsigned diff;
|
2013-07-08 17:11:44 +02:00
|
|
|
int i;
|
2013-07-09 03:19:22 +02:00
|
|
|
|
|
|
|
if (!dbg_info->ehci_debug)
|
|
|
|
return;
|
|
|
|
|
|
|
|
diff = (unsigned)dbg_info->ehci_caps - ehci_base;
|
|
|
|
dbg_info->ehci_regs -= diff;
|
|
|
|
dbg_info->ehci_debug -= diff;
|
|
|
|
dbg_info->ehci_caps = (void*)ehci_base;
|
2013-07-08 17:11:44 +02:00
|
|
|
|
|
|
|
for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
|
|
|
|
dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED;
|
2013-07-09 03:19:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void usbdebug_disable(void)
|
|
|
|
{
|
2013-07-11 06:49:46 +02:00
|
|
|
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
|
2013-07-08 17:11:44 +02:00
|
|
|
int i;
|
|
|
|
for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
|
|
|
|
dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED;
|
2013-07-09 03:19:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_ehci_set_resources(struct device *dev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
|
|
|
|
usbdebug_disable();
|
|
|
|
|
|
|
|
if (ehci_drv_ops->set_resources)
|
|
|
|
ehci_drv_ops->set_resources(dev);
|
|
|
|
res = find_resource(dev, EHCI_BAR_INDEX);
|
|
|
|
if (!res)
|
|
|
|
return;
|
|
|
|
|
|
|
|
usbdebug_re_enable((u32)res->base);
|
|
|
|
report_resource_stored(dev, res, "");
|
|
|
|
printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_ehci_read_resources(struct device *dev)
|
|
|
|
{
|
|
|
|
if (!ehci_drv_ops) {
|
|
|
|
memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
|
|
|
|
ehci_drv_ops = dev->ops;
|
|
|
|
ehci_dbg_ops.set_resources = pci_ehci_set_resources;
|
|
|
|
dev->ops = &ehci_dbg_ops;
|
|
|
|
printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
|
|
|
|
} else {
|
|
|
|
printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_dev_read_resources(dev);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
int dbgp_ep_is_active(struct dbgp_pipe *pipe)
|
2013-07-05 20:38:54 +02:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED);
|
2011-01-28 09:05:54 +01:00
|
|
|
}
|
2013-07-06 10:56:49 +02:00
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
struct dbgp_pipe *dbgp_console_output(void)
|
2013-07-06 10:56:49 +02:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT];
|
2013-07-11 06:49:46 +02:00
|
|
|
}
|
|
|
|
|
2013-07-08 17:11:44 +02:00
|
|
|
struct dbgp_pipe *dbgp_console_input(void)
|
2013-07-11 06:49:46 +02:00
|
|
|
{
|
2013-07-08 17:11:44 +02:00
|
|
|
return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN];
|
2013-07-06 10:56:49 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
int usbdebug_init(void)
|
|
|
|
{
|
2013-07-11 06:49:46 +02:00
|
|
|
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
|
2013-07-06 10:41:09 +02:00
|
|
|
|
2013-07-06 10:56:49 +02:00
|
|
|
#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE
|
|
|
|
enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
|
|
|
|
#endif
|
|
|
|
return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
|
|
|
|
}
|