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coreboot-kgpe-d16/util/amdfwtool/amdfwtool.h

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amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _AMD_FW_TOOL_H_
#define _AMD_FW_TOOL_H_
util/amdfwtool: Include the header with __packed definition Checkpatch script recommends to use __packed instead of __attribute__((packed)). Currently the build rule for amdfwtool does not include the required header file with __packed definition. Update the compiler flag to include the required header file. BUG=None TEST=Build amdfwtool. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06 22:02:41 +02:00
#include <commonlib/bsd/compiler.h>
util/amdfwtool/amdfwtool: Don't rewrite macros Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 09:58:29 +02:00
#include <commonlib/bsd/helpers.h>
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
#include <openssl/sha.h>
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
#include <stdint.h>
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
#include <stdbool.h>
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
amdfwtool: Move some funtions to other categorized source files To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-22 05:50:36 +01:00
#define ERASE_ALIGNMENT 0x1000U
#define TABLE_ALIGNMENT 0x1000U
#define BLOB_ALIGNMENT 0x100U
#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
enum platform {
PLATFORM_UNKNOWN,
PLATFORM_CARRIZO,
PLATFORM_STONEYRIDGE,
PLATFORM_RAVEN,
PLATFORM_PICASSO,
PLATFORM_RENOIR,
PLATFORM_CEZANNE,
PLATFORM_MENDOCINO,
PLATFORM_LUCIENNE,
PLATFORM_PHOENIX,
PLATFORM_GLINDA
};
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
typedef enum _amd_fw_type {
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
AMD_FW_PSP_PUBKEY = 0x00,
AMD_FW_PSP_BOOTLOADER = 0x01,
AMD_FW_PSP_SECURED_OS = 0x02,
AMD_FW_PSP_RECOVERY = 0x03,
AMD_FW_PSP_NVRAM = 0x04,
AMD_FW_PSP_RTM_PUBKEY = 0x05,
AMD_FW_PSP_SMU_FIRMWARE = 0x08,
AMD_FW_PSP_SECURED_DEBUG = 0x09,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_ABL_PUBKEY = 0x0a,
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
AMD_PSP_FUSE_CHAIN = 0x0b,
AMD_FW_PSP_TRUSTLETS = 0x0c,
AMD_FW_PSP_TRUSTLETKEY = 0x0d,
AMD_FW_PSP_SMU_FIRMWARE2 = 0x12,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_DEBUG_UNLOCK = 0x13,
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
AMD_BOOT_DRIVER = 0x1b,
AMD_SOC_DRIVER = 0x1c,
AMD_DEBUG_DRIVER = 0x1d,
AMD_INTERFACE_DRIVER = 0x1f,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_HW_IPCFG = 0x20,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_WRAPPED_IKEK = 0x21,
AMD_TOKEN_UNLOCK = 0x22,
AMD_SEC_GASKET = 0x24,
AMD_MP2_FW = 0x25,
AMD_DRIVER_ENTRIES = 0x28,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_FW_KVM_IMAGE = 0x29,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_MP5 = 0x2a,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_S0I3_DRIVER = 0x2d,
AMD_ABL0 = 0x30,
AMD_ABL1 = 0x31,
AMD_ABL2 = 0x32,
AMD_ABL3 = 0x33,
AMD_ABL4 = 0x34,
AMD_ABL5 = 0x35,
AMD_ABL6 = 0x36,
AMD_ABL7 = 0x37,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_SEV_DATA = 0x38,
AMD_SEV_CODE = 0x39,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_FW_PSP_WHITELIST = 0x3a,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_VBIOS_BTLOADER = 0x3c,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_FW_L2_PTR = 0x40,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_DXIO = 0x42,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_FW_USB_PHY = 0x44,
AMD_FW_TOS_SEC_POLICY = 0x45,
AMD_FW_DRTM_TA = 0x47,
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
AMD_FW_RECOVERYAB_A = 0x48,
AMD_FW_RECOVERYAB_B = 0x4A,
AMD_FW_BIOS_TABLE = 0x49,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_FW_KEYDB_BL = 0x50,
AMD_FW_KEYDB_TOS = 0x51,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_FW_PSP_VERSTAGE = 0x52,
AMD_FW_VERSTAGE_SIG = 0x53,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_RPMC_NVRAM = 0x54,
amdfwtool: Add SPL support SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-27 15:38:27 +01:00
AMD_FW_SPL = 0x55,
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
AMD_FW_DMCU_ERAM = 0x58,
AMD_FW_DMCU_ISR = 0x59,
util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-24 02:04:51 +01:00
AMD_FW_MSMU = 0x5a,
AMD_FW_SPIROM_CFG = 0x5c,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_MPIO = 0x5d,
util/amdfwtool: add comment about reused PSP firmware type 0x5f On family 15h and 16h processors with PSP, the PSP firmware type 0x5f corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to clarify this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-01 19:21:11 +01:00
AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */
AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */
util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-24 02:04:51 +01:00
AMD_FW_DMCUB = 0x71,
amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-02 11:48:23 +01:00
AMD_FW_PSP_BOOTLOADER_AB = 0x73,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_RIB = 0x76,
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
AMD_FW_AMF_SRAM = 0x85,
AMD_FW_AMF_DRAM = 0x86,
AMD_FW_AMF_WLAN = 0x88,
AMD_FW_AMF_MFD = 0x89,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_MPDMA_TF = 0x8c,
util/amdfwtool: Add IKEK key for Trusted Application This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-04 02:16:34 +02:00
AMD_TA_IKEK = 0x8d,
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
AMD_FW_MPCCX = 0x90,
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
AMD_FW_GMI3_PHY = 0x91,
AMD_FW_MPDMA_PM = 0x92,
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
AMD_FW_LSDMA = 0x94,
AMD_FW_C20_MP = 0x95,
AMD_FW_FCFG_TABLE = 0x98,
AMD_FW_MINIMSMU = 0x9a,
AMD_FW_SRAM_FW_EXT = 0x9d,
util/amdfwtool: Add UMSMU blob support Add PSP blob Type 0xA2 uMsmu support. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-07 18:12:40 +01:00
AMD_FW_UMSMU = 0xa2,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */
AMD_FW_GEC,
AMD_FW_XHCI,
AMD_FW_INVALID, /* Real last one to detect the last entry in table. */
AMD_FW_SKIP /* This is for non-applicable options. */
} amd_fw_type;
typedef enum _amd_bios_type {
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
AMD_BIOS_RTM_PUBKEY = 0x05,
AMD_BIOS_SIG = 0x07,
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
AMD_BIOS_APCB = 0x60,
AMD_BIOS_APOB = 0x61,
AMD_BIOS_BIN = 0x62,
AMD_BIOS_APOB_NV = 0x63,
AMD_BIOS_PMUI = 0x64,
AMD_BIOS_PMUD = 0x65,
AMD_BIOS_UCODE = 0x66,
AMD_BIOS_APCB_BK = 0x68,
AMD_BIOS_MP2_CFG = 0x6a,
AMD_BIOS_PSP_SHARED_MEM = 0x6b,
AMD_BIOS_L2_PTR = 0x70,
AMD_BIOS_INVALID,
AMD_BIOS_SKIP
} amd_bios_type;
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
typedef enum _amd_addr_mode {
AMD_ADDR_PHYSICAL = 0, /* Physical address */
AMD_ADDR_REL_BIOS, /* Relative to beginning of image */
AMD_ADDR_REL_TAB, /* Relative to table */
AMD_ADDR_REL_SLOT, /* Relative to slot */
} amd_addr_mode;
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
struct second_gen_efs { /* todo: expand for Server products */
int gen:1; /* Client products only use bit 0 */
int reserved:31;
} __attribute__((packed));
#define EFS_SECOND_GEN 0
amdfwtool: Add a macro to set explicitly second gen for old SOCs It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:50:07 +02:00
#define EFS_BEFORE_SECOND_GEN 1
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
typedef struct _embedded_firmware {
uint32_t signature; /* 0x55aa55aa */
uint32_t imc_entry;
uint32_t gec_entry;
uint32_t xhci_entry;
util/amdfwtool: rename PSP related embedded_firmware struct elements The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-18 14:00:35 +02:00
uint32_t psp_directory;
util/amdfwtool: remove unused union from embedded_firmware struct Since commit 2f6b7d557d97 ("amdfwtool: Move the filling of table headers into functions"), the combo_psp_directory union element in the embedded_firmware is unused and the new_psp_directory element is used in all places, so replace the union of new_psp_directory and combo_psp_directory with just the new_psp_directory struct element. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20 16:02:47 +01:00
uint32_t new_psp_directory; /* also used as combo_psp_directory */
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
uint32_t bios0_entry; /* todo: add way to select correct entry */
uint32_t bios1_entry;
uint32_t bios2_entry;
struct second_gen_efs efs_gen;
uint32_t bios3_entry;
uint32_t reserved_2Ch;
uint32_t promontory_fw_ptr;
uint32_t lp_promontory_fw_ptr;
uint32_t reserved_38h;
uint32_t reserved_3Ch;
uint8_t spi_readmode_f15_mod_60_6f;
uint8_t fast_speed_new_f15_mod_60_6f;
uint8_t reserved_42h;
uint8_t spi_readmode_f17_mod_00_2f;
uint8_t spi_fastspeed_f17_mod_00_2f;
uint8_t qpr_dummy_cycle_f17_mod_00_2f;
uint8_t reserved_46h;
uint8_t spi_readmode_f17_mod_30_3f;
uint8_t spi_fastspeed_f17_mod_30_3f;
uint8_t micron_detect_f17_mod_30_3f;
uint8_t reserved_4Ah;
uint8_t reserved_4Bh;
uint32_t reserved_4Ch;
} __attribute__((packed, aligned(16))) embedded_firmware;
typedef struct _psp_directory_header {
uint32_t cookie;
uint32_t checksum;
uint32_t num_entries;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
union {
uint32_t additional_info;
struct {
uint32_t dir_size:10;
uint32_t spi_block_size:4;
uint32_t base_addr:15;
uint32_t address_mode:2;
uint32_t not_used:1;
} __attribute__((packed)) additional_info_fields;
};
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
} __attribute__((packed, aligned(16))) psp_directory_header;
typedef struct _psp_directory_entry {
uint8_t type;
uint8_t subprog;
amdfwtool: Add definition of instance for PSP entry Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-16 14:18:40 +02:00
union {
uint16_t rsvd;
struct {
uint8_t rom_id:2;
uint8_t writable:1;
uint8_t inst:4;
uint8_t rsvd_1:1;
uint8_t rsvd_2:8;
} __attribute__((packed));
};
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
uint32_t size;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
uint64_t addr:62; /* or a value in some cases */
uint64_t address_mode:2;
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
} __attribute__((packed)) psp_directory_entry;
typedef struct _psp_directory_table {
psp_directory_header header;
psp_directory_entry entries[];
} __attribute__((packed, aligned(16))) psp_directory_table;
amdfwtool: Increase MAX_PSP_ENTRIES The MAX_PSP_ENTRIES constant reserves space for the psp directory table entries. This table is aligned to 4K and the next binary is also aligned to 4K. The number of psp directory entries on Birman exceeds the previous limit, so increase it to the maximum that will fit in a 4K block. TEST=timeless builds for Birman unchanged Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-09 18:33:52 +01:00
#define MAX_PSP_ENTRIES 0xff
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
typedef struct _psp_combo_header {
uint32_t cookie;
uint32_t checksum;
uint32_t num_entries;
uint32_t lookup;
uint64_t reserved[2];
} __attribute__((packed, aligned(16))) psp_combo_header;
typedef struct _psp_combo_entry {
uint32_t id_sel;
uint32_t id;
uint64_t lvl2_addr;
} __attribute__((packed)) psp_combo_entry;
typedef struct _psp_combo_directory {
psp_combo_header header;
psp_combo_entry entries[];
} __attribute__((packed, aligned(16))) psp_combo_directory;
amdfwtool: Add combo index and combo config table For now, combo index is 0, and only the first entry in config table is used. The index will grow when there are more combo entries. Add a command parameter to give fw.cfg for combo index 1. Process the combo config in the future loop. Change-Id: I00609d91defc08e17f937ac8339575f84b1bd37c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-07 08:28:57 +01:00
#define MAX_COMBO_ENTRIES 2
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
typedef struct _bios_directory_hdr {
uint32_t cookie;
uint32_t checksum;
uint32_t num_entries;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
union {
uint32_t additional_info;
struct {
uint32_t dir_size:10;
uint32_t spi_block_size:4;
uint32_t base_addr:15;
uint32_t address_mode:2;
uint32_t not_used:1;
} __attribute__((packed)) additional_info_fields;
};
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
} __attribute__((packed, aligned(16))) bios_directory_hdr;
typedef struct _bios_directory_entry {
uint8_t type;
uint8_t region_type;
int reset:1;
int copy:1;
int ro:1;
int compressed:1;
int inst:4;
uint8_t subprog; /* b[7:3] reserved */
uint32_t size;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
uint64_t source:62;
uint64_t address_mode:2;
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
uint64_t dest;
} __attribute__((packed)) bios_directory_entry;
typedef struct _bios_directory_table {
bios_directory_hdr header;
bios_directory_entry entries[];
} bios_directory_table;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supported Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 19:26:31 +01:00
#define MAX_BIOS_ENTRIES 0x2f
amdfwtool: Change the definition of level to a bitwise form Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 10:53:23 +02:00
#define BDT_LVL1 (1 << 0)
#define BDT_LVL2 (1 << 1)
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
#define BDT_LVL1_AB (1 << 2)
#define BDT_LVL2_AB (1 << 3)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
#define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
typedef struct _amd_bios_entry {
amd_bios_type type;
char *filename;
int subpr;
int region_type;
int reset;
int copy;
int ro;
int zlib;
int inst;
uint64_t src;
uint64_t dest;
size_t size;
int level;
} amd_bios_entry;
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
typedef struct _ish_directory_table {
uint32_t checksum;
uint32_t boot_priority;
uint32_t update_retry_count;
uint8_t glitch_retry_count;
uint8_t glitch_higherbits_reserved[3];
uint32_t pl2_location;
uint32_t psp_id;
uint32_t slot_max_size;
uint32_t reserved;
} __attribute__((packed)) ish_directory_table;
amdfwtool: Move EFS related definitions to header file EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-26 04:16:33 +02:00
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
#define PSP_COOKIE 0x50535024 /* 'PSP$' */
#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
#define BHD_COOKIE 0x44484224 /* 'DHB$ */
#define BHDL2_COOKIE 0x324c4224 /* '2LB$ */
amdfwtool: combo: Add combo feature for BIOS table It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:54:47 +02:00
#define BHD2_COOKIE 0x44484232 /* 'DHB2' */
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amdfwtool: Change the definition of level to a bitwise form Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 10:53:23 +02:00
#define PSP_LVL1 (1 << 0)
#define PSP_LVL2 (1 << 1)
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
#define PSP_LVL1_AB (1 << 2)
#define PSP_LVL2_AB (1 << 3)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
#define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB)
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
typedef struct _amd_fw_entry_hash {
uint16_t fw_id;
uint16_t subtype;
uint32_t sha_len;
uint8_t sha[SHA384_DIGEST_LENGTH];
} amd_fw_entry_hash;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
typedef struct _amd_fw_entry {
amd_fw_type type;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* Mendocino and later SoCs use fw_id instead of fw_type. fw_type is still around
for backwards compatibility. fw_id can be populated from the PSP binary file. */
uint16_t fw_id;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
char *filename;
uint8_t subprog;
amdfwtool: Add definition of instance for PSP entry Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-16 14:18:40 +02:00
uint8_t inst;
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
uint64_t dest;
size_t size;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
int level;
uint64_t other;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* If the binary is signed and the tool is invoked to keep the signed binaries separate,
then this field is populated with the offset of the concerned PSP binary (relative to
BIOS or PSP Directory table). */
uint64_t addr_signed;
uint32_t file_size;
/* Some files that don't have amd_fw_header have to be skipped from hashing. These files
include but not limited to: *iKek*, *.tkn, *.stkn */
bool skip_hashing;
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
uint32_t num_hash_entries;
amd_fw_entry_hash *hash_entries;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} amd_fw_entry;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* Most PSP binaries, if not all, have the following header format. */
struct amd_fw_header {
uint8_t reserved_0[20];
uint32_t fw_size_signed;
uint8_t reserved_18[24];
/* 1 if the image is signed, 0 otherwise */
uint32_t sig_opt;
uint32_t sig_id;
uint8_t sig_param[16];
uint32_t comp_opt;
uint8_t reserved_4c[4];
uint32_t uncomp_size;
uint32_t comp_size;
/* Starting MDN fw_id is populated instead of fw_type. */
uint16_t fw_id;
uint8_t reserved_5a[18];
uint32_t size_total;
uint8_t reserved_70[12];
/* Starting MDN fw_id is populated instead of fw_type. fw_type will still be around
for backwards compatibility. */
uint8_t fw_type;
uint8_t fw_subtype;
uint8_t fw_subprog;
uint8_t reserved_7f;
uint8_t reserved_80[128];
} __packed;
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
struct psp_fw_hash_table {
uint16_t version;
uint16_t no_of_entries_256;
uint16_t no_of_entries_384;
/* The next 2 elements are pointers to arrays of SHA256 and SHA384 entries. */
/* It does not make sense to store pointers in the CBFS file */
} __packed;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
typedef struct _amd_cb_config {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
bool have_whitelist;
bool unlock_secure;
bool use_secureos;
bool load_mp2_fw;
bool multi_level;
bool s0i3;
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
bool second_gen;
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
bool have_mb_spl;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
bool recovery_ab;
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
bool recovery_ab_single_copy;
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
bool need_ish;
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
bool use_combo;
util/amdfwtool: Support not passing recovery/backup APCB If Recovery/Backup APCB is not passed, then AMD_BIOS_APCB_BK entry is not populated. But PSP expects that bios directory entry to be populated. Also on mainboards where both APCB and recovery APCB are same (eg. Skyrim), 2 copies of the same APCB are added to amdfw*.rom. Update amdfwtool to support not passing recovery/backup APCB. If the recovery APCB is not passed, then populate AMD_BIOS_APCB_BK entry and make it point to the same offset as AMD_BIOS_APCB entry. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Ensure that the device can enter recovery mode. Perform multiple suspend/resume cycles. Change-Id: I031ba817573cd35160f5e219b1b373ddce69aa6b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73661 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10 01:39:31 +01:00
bool have_apcb_bk;
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
enum platform soc_id;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} amd_cb_config;
void register_fw_fuse(char *str);
amdfwtool: Remove the option --list which nobody uses It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09 04:43:55 +01:00
uint8_t process_config(FILE *config, amd_cb_config *cb_config);
amdfwtool: Move some funtions to other categorized source files To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-22 05:50:36 +01:00
void process_signed_psp_firmwares(const char *signed_rom,
amd_fw_entry *fw_table,
uint64_t signed_start_addr,
enum platform soc_id);
void write_or_fail(int fd, void *ptr, size_t size);
ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size);
ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#define OK 0
#define LINE_EOF (1)
#define LINE_TOO_LONG (2)
#endif /* _AMD_FW_TOOL_H_ */