coreboot-kgpe-d16/src/soc/ucb/riscv/cbmem.c

/* SPDX-License-Identifier: GPL-2.0-only */

#include <cbmem.h>
#include <symbols.h>
#include <ramdetect.h>

void *cbmem_top_chipset(void)
{
	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
}
soc/ucb: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1b7a4fd5c6049230799d9e77903382812bc9768d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> 2020-04-04 18:51:34 +02:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00
			`#include <cbmem.h>`
lib: Rewrite qemu-armv7 ramdetect * Move armv7 RAM dection to a common place * Enable it for all emulated platforms * Use 32bit probe values and restore memory even on failure * Use the new logic on the following boards: qemu-armv7 qemu-riscv Tested on qemu-system-riscv: Fixes kernel panic due to wrong memory limits reported. Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> 2019-06-30 22:12:15 +02:00			`#include <symbols.h>`
			`#include <ramdetect.h>`
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00
lib/cbmem_top: Add a common cbmem_top implementation This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> 2019-10-23 17:25:58 +02:00			`void *cbmem_top_chipset(void)`
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00			`{`
lib: Rewrite qemu-armv7 ramdetect * Move armv7 RAM dection to a common place * Enable it for all emulated platforms * Use 32bit probe values and restore memory even on failure * Use the new logic on the following boards: qemu-armv7 qemu-riscv Tested on qemu-system-riscv: Fixes kernel panic due to wrong memory limits reported. Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> 2019-06-30 22:12:15 +02:00			`return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);`
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00			`}`