lib/cbmem_top: Add a common cbmem_top implementation

This adds a common cbmem_top implementation to all coreboot target.

In romstage a static variable will be used to cache the result of
cbmem_top_romstage.

In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable
needs to be populated by the stage entry with the value passed via the
calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the
same implementation as will be used as in romstage.

Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/arch/x86/cbmem.c

@@ -16,7 +16,7 @@
 
 #if CONFIG(CBMEM_TOP_BACKUP)
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	static void *cbmem_top_backup;
 	void *top_backup;

src/cpu/amd/family_10h-family_15h/ram_calc.c

@@ -86,7 +86,7 @@ uint64_t get_cc6_memory_size()
 	return cc6_size;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uint32_t topmem = rdmsr(TOP_MEM).lo;
 

src/cpu/ti/am335x/cbmem.c

@@ -15,7 +15,7 @@
 #include <cbmem.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (CONFIG_DRAM_SIZE_MB << 20);
 }

src/include/cbmem.h

@@ -73,7 +73,18 @@ void cbmem_top_init(void);
  * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no
  * upper limit. This should not be called before memory is initialized.
  */
+/* The assumption is made that the result of cbmem_top_romstage fits in the size
+   of uintptr_t in the ramstage. */
+extern uintptr_t _cbmem_top_ptr;
 void *cbmem_top(void);
+/* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via
+ * calling arguments to the next stage and saved in the global _cbmem_top_ptr
+ * global variable. Only a romstage callback needs to be implemented by the
+ * platform. It is up to the stages after romstage to save the calling argument
+ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same
+ * implementation as used in romstage will be used.
+ */
+void *cbmem_top_chipset(void);
 
 /* Add a cbmem entry of a given size and id. These return NULL on failure. The
  * add function performs a find first and do not check against the original

src/lib/Kconfig

@@ -24,6 +24,12 @@ config RAMSTAGE_LIBHWBASE
 	help
 	  Selected by features that require `libhwbase` in ramstage.
 
+config RAMSTAGE_CBMEM_TOP_ARG
+	bool
+	help
+	  Select this if stages run after romstage get the cbmem_top
+	  pointer as the function arguments when called from romstage.
+
 config FLATTENED_DEVICE_TREE
 	bool
 	help

src/lib/imd_cbmem.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <assert.h>
 #include <boot/coreboot_tables.h>
 #include <bootstate.h>
 #include <bootmem.h>
@@ -44,6 +45,28 @@
 	(!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \
 	 !CONFIG(CAR_GLOBAL_MIGRATION))
 
+/* The program loader passes on cbmem_top and the program entry point
+   has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */
+uintptr_t _cbmem_top_ptr;
+
+void *cbmem_top(void)
+{
+	if (ENV_ROMSTAGE
+	    || ((ENV_POSTCAR || ENV_RAMSTAGE)
+		&& !CONFIG(RAMSTAGE_CBMEM_TOP_ARG))) {
+		MAYBE_STATIC_BSS void *top = NULL;
+		if (top)
+			return top;
+		top = cbmem_top_chipset();
+		return top;
+	}
+	if ((ENV_POSTCAR || ENV_RAMSTAGE) && CONFIG(RAMSTAGE_CBMEM_TOP_ARG))
+		return (void *)_cbmem_top_ptr;
+
+	dead_code();
+}
+
+
 static inline struct imd *cbmem_get_imd(void)
 {
 	if (CAN_USE_GLOBALS) {

src/mainboard/emulation/qemu-aarch64/cbmem.c

@@ -10,7 +10,7 @@
 #include <ramdetect.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
 }

src/mainboard/emulation/qemu-armv7/cbmem.c

@@ -15,7 +15,7 @@
 #include <symbols.h>
 #include <ramdetect.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
 }

src/mainboard/emulation/qemu-i440fx/memmap.c

@@ -52,7 +52,7 @@ unsigned long qemu_get_memory_size(void)
 	return tomk;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top = 0;
 

src/mainboard/emulation/qemu-power8/cbmem.c

@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
 	/* For now, last 1M of 4G */

src/northbridge/intel/e7505/memmap.c

@@ -21,7 +21,7 @@
 #include <program_loading.h>
 #include "e7505.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	uintptr_t tolm;

src/northbridge/intel/fsp_rangeley/memmap.c

@@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
 }

src/northbridge/intel/gm45/memmap.c

@@ -117,7 +117,7 @@ static size_t northbridge_get_tseg_size(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;

src/northbridge/intel/haswell/memmap.c

@@ -34,7 +34,7 @@ static uintptr_t smm_region_start(void)
 	return tom & ~((1 << 20) - 1);
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)smm_region_start();
 }

src/northbridge/intel/i440bx/memmap.c

@@ -23,7 +23,7 @@
 #include <program_loading.h>
 #include "i440bx.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Base of TSEG is top of usable DRAM */
 	/*

src/northbridge/intel/i945/memmap.c

@@ -71,7 +71,7 @@ static size_t northbridge_get_tseg_size(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;

src/northbridge/intel/nehalem/memmap.c

@@ -42,7 +42,7 @@ static size_t northbridge_get_tseg_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }

src/northbridge/intel/pineview/memmap.c

@@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;

src/northbridge/intel/sandybridge/memmap.c

@@ -31,7 +31,7 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }

src/northbridge/intel/x4x/memmap.c

@@ -128,7 +128,7 @@ static uintptr_t northbridge_get_tseg_base(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;

src/northbridge/via/vx900/memmap.c

@@ -120,7 +120,7 @@ u32 vx900_get_tolm(void)
 	return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t tolm;
 	uintptr_t fb_size;

src/soc/amd/picasso/memmap.c

@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
 	*size = BERT_REGION_MAX_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
 

src/soc/amd/stoneyridge/memmap.c

@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
 	*size = BERT_REGION_MAX_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
 

src/soc/cavium/cn81xx/cbmem.c

@@ -20,7 +20,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Make sure not to overlap with reserved ATF scratchpad */
 	return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB);

src/soc/imgtec/pistachio/cbmem.c

@@ -18,7 +18,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (CONFIG_DRAM_SIZE_MB << 20);
 }

src/soc/intel/apollolake/memmap.c

@@ -20,7 +20,7 @@
 
 #include "chip.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	const config_t *config;
 	void *tolum = (void *)sa_get_tseg_base();

src/soc/intel/baytrail/memmap.c

@@ -29,7 +29,7 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }

src/soc/intel/braswell/memmap.c

@@ -33,7 +33,7 @@ void smm_region(uintptr_t *start, size_t *size)
 	*size = smm_region_size();
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t smm_base;
 	size_t smm_size;

src/soc/intel/broadwell/memmap.c

@@ -41,7 +41,7 @@ static uintptr_t dpr_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) dpr_region_start();
 }

src/soc/intel/cannonlake/memmap.c

@@ -247,7 +247,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 

src/soc/intel/denverton_ns/memmap.c

@@ -60,7 +60,7 @@ u32 top_of_32bit_ram(void)
 	       power_of_2(iqat_region_size + tseg_region_size);
 }
 
-void *cbmem_top(void) { return (void *)top_of_32bit_ram(); }
+void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); }
 
 static inline uintptr_t smm_region_start(void)
 {

src/soc/intel/fsp_baytrail/memmap.c

@@ -40,7 +40,7 @@ static size_t smm_region_size(void)
  * @return pointer to the first byte of reserved memory
  */
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
 }

src/soc/intel/fsp_broadwell_de/memmap.c

@@ -23,7 +23,7 @@
 #include <soc/pci_devs.h>
 #include <device/pci_ops.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
 }

src/soc/intel/icelake/memmap.c

@@ -226,7 +226,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 

src/soc/intel/quark/memmap.c

@@ -18,7 +18,7 @@
 #include <cbmem.h>
 #include <soc/reg_access.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uint32_t top_of_memory;
 

src/soc/intel/skylake/memmap.c

@@ -248,7 +248,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 

src/soc/mediatek/common/cbmem.c

@@ -21,7 +21,7 @@
 
 #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
 }

src/soc/nvidia/tegra124/cbmem.c

@@ -17,7 +17,7 @@
 #include <soc/display.h>
 #include <soc/sdram.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
 }

src/soc/nvidia/tegra210/cbmem.c

@@ -16,7 +16,7 @@
 #include <cbmem.h>
 #include <soc/addressmap.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	static uintptr_t addr;
 

src/soc/qualcomm/ipq40xx/cbmem.c

@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before

src/soc/qualcomm/ipq806x/cbmem.c

@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before

src/soc/qualcomm/qcs405/cbmem.c

@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)3 * GiB);
 }

src/soc/qualcomm/sc7180/cbmem.c

@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)4 * GiB);
 }

src/soc/qualcomm/sdm845/cbmem.c

@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)4 * GiB);
 }

src/soc/rockchip/common/cbmem.c

@@ -19,7 +19,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
 			   MAX_DRAM_ADDRESS);

src/soc/samsung/exynos5250/cbmem.c

@@ -17,7 +17,7 @@
 #include <cbmem.h>
 #include <soc/cpu.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)(get_fb_base_kb() * KiB);
 }

src/soc/samsung/exynos5420/cbmem.c

@@ -17,7 +17,7 @@
 #include <soc/cpu.h>
 #include <stddef.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)(get_fb_base_kb() * KiB);
 }

src/soc/sifive/fu540/cbmem.c

@@ -19,7 +19,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
 			   FU540_MAXDRAM);

src/soc/ucb/riscv/cbmem.c

@@ -15,7 +15,7 @@
 #include <symbols.h>
 #include <ramdetect.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
 }