52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 2
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*/
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#include <device/pci.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/pcr_ids.h>
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#include <soc/soc_chip.h>
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/*
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* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
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* certain memory range as reserved range for BIOS usage.
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* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
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*/
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static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = {
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{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
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{
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return lpc_fixed_mmio_ranges;
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}
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void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
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{
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const config_t *config = config_of(dev);
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
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{
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/* Mirror these same settings in DMI PCR */
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
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}
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