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Cosmetics, fix typos (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-21 19:37:23 +01:00
##
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
## Copyright (C) 2008 coresystems GmbH
Cosmetics, fix typos (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-21 19:37:23 +01:00
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
## 3. The name of the author may not be used to endorse or promote products
## derived from this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
mainmenu "Libpayload Configuration"
libpayload update * rework Config.in * add string_to_args function to actually make getopt usable. * add strchr * add strlcat * some malloc fixes (exposed by the USB stack) * add malloc debugging (thanks to Matthias Krause from Secunet!) * make LAR support optional, it's not really used anymore * (define htoX macros for ppc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 23:15:19 +01:00
menu "Generic Options"
libpayload: Introduce new Kconfig to explicitly allow GPL code There have been leaks of GPL code into libpayload for a while now, for new features or improvements that require third party code with no adequate alternative among BSD-licensed software. It seems silly and counter-productive to keep holding back features and performance improvements from libpayload for a use-case (proprietary payloads) that doesn't even seem to be implemented anywhere to date. Open-source payloads should not need to suffer to appease commercial ones. Instead, this patch introduces a new Kconfig option to explicitly allow inclusion of GPL code. It will use Kconfig dependencies and/or Makefile rules to ensure that no GPL code can end up in the final payload if that option is unset, allowing proprietary payloads to keep working with the existing BSD-licensed feature set. New features and patches (that are sufficiently separate and self-contained to allow guarding through this config option) can choose whether to import GPL code, and need to depend on this option if they do. Also clean up all (known) existing uses of GPL code to depend on the new option, add some recent third-party imports to the LICENSES file, and relicense the selfboot.c files to BSD with permission of the author. BUG=chrome-os-partner:24957 TEST=Compiled Falco and Nyan_Big both with and without the new option, disassembled output binaries to ensure that memcpy() looks as expected. Original-Change-Id: I6e3a75b1a8e46291c75a876844c7a01f7d3f2a0e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203513 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d8e5a9fdf583b5ac861f34baea6a16c4d8536512) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I446fef028264c793b946dd9f765e446bf708b4db Reviewed-on: http://review.coreboot.org/8118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-11 23:16:35 +02:00
config GPL
bool "GPLv2-licensed Options"
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if CHROMEOS
libpayload: Introduce new Kconfig to explicitly allow GPL code There have been leaks of GPL code into libpayload for a while now, for new features or improvements that require third party code with no adequate alternative among BSD-licensed software. It seems silly and counter-productive to keep holding back features and performance improvements from libpayload for a use-case (proprietary payloads) that doesn't even seem to be implemented anywhere to date. Open-source payloads should not need to suffer to appease commercial ones. Instead, this patch introduces a new Kconfig option to explicitly allow inclusion of GPL code. It will use Kconfig dependencies and/or Makefile rules to ensure that no GPL code can end up in the final payload if that option is unset, allowing proprietary payloads to keep working with the existing BSD-licensed feature set. New features and patches (that are sufficiently separate and self-contained to allow guarding through this config option) can choose whether to import GPL code, and need to depend on this option if they do. Also clean up all (known) existing uses of GPL code to depend on the new option, add some recent third-party imports to the LICENSES file, and relicense the selfboot.c files to BSD with permission of the author. BUG=chrome-os-partner:24957 TEST=Compiled Falco and Nyan_Big both with and without the new option, disassembled output binaries to ensure that memcpy() looks as expected. Original-Change-Id: I6e3a75b1a8e46291c75a876844c7a01f7d3f2a0e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203513 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d8e5a9fdf583b5ac861f34baea6a16c4d8536512) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I446fef028264c793b946dd9f765e446bf708b4db Reviewed-on: http://review.coreboot.org/8118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-11 23:16:35 +02:00
default n
help
Prompt for options that will build code licensed under the GNU General
Public License (version 2). This will subject the whole payload to the
terms of this license (including its provision to release all sources,
please see the LICENSE_GPL file for details).
libpayload update * rework Config.in * add string_to_args function to actually make getopt usable. * add strchr * add strlcat * some malloc fixes (exposed by the USB stack) * add malloc debugging (thanks to Matthias Krause from Secunet!) * make LAR support optional, it's not really used anymore * (define htoX macros for ppc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 23:15:19 +01:00
config EXPERIMENTAL
bool "Experimental Options"
default n
help
Prompt for experimental functionality. Attention: This is not likely
to work without problems
config DEVELOPER
bool "Developer Options"
default n
help
Prompt for developer options. These options are only interesting for
libpayload developers.
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
config CHROMEOS
treewide: Unify Google branding Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-28 18:36:23 +02:00
bool "ChromeOS Options"
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default n
help
treewide: Unify Google branding Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-28 18:36:23 +02:00
Select configuration defaults appropriate for ChromeOS boards.
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
libpayload: Add compiler switch clang is totally untested, but it mirrors coreboot now. Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10800 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 11:04:42 +02:00
choice
prompt "Compiler to use"
default COMPILER_GCC
help
This option allows you to select the compiler.
config COMPILER_GCC
bool "GCC"
help
Use the GNU Compiler Collection (GCC).
config COMPILER_LLVM_CLANG
bool "LLVM/clang"
help
Use LLVM/clang.
endchoice
libpayload: Add support for link time optimization Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 114 KiB 11.49s LTO 95 KiB 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38291 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 02:55:07 +02:00
config LTO
bool "Use link time optimization (LTO)"
default n
depends on COMPILER_GCC
help
Compile with link time optimization. This can often decrease the
final binary size, but may increase compilation time.
libpayload: Add remote GDB support This patch adds the ability to attach a GDB host through the UART to a running payload. Libpayload implements a small stub that can parse and respond to the GDB remote protocol and provide the required primitives (reading/writing registers/memory, etc.) to allow GDB to control execution. The goal of this implementation is to be as small and uninvasive as possible. It implements only the minimum amount of primitives required, and relies on GDB's impressive workaround capabilities (such as emulating breakpoints by temporarily replacing instructions) for the more complicated features. This way, a relatively tiny amount of code on the firmware side opens a vast range of capabilities to the user, not just in debugging but also in remote-controlling the firmware to change its behavior (e.g. through GDBs ability to modify variables and call functions). By default, a system with the REMOTEGDB Kconfig will only trap into GDB when executing halt() (including the calls from die_if(), assert(), and exception handlers). In addition, payloads can manually call gdb_enter() if desired. It will print a final "Ready for GDB connection." on the serial, detach the normal serial output driver and wait for the commands that GDB starts sending on attach. Based on original implementation by Gabe Black <gabeblack@chromium.org>. BUG=chrome-os-partner:18390 TEST=Boot a GDB enabled image in recovery mode (or get it to hit a halt()), close your terminal, execute '<toolchain>-gdb --symbols /build/<board>/firmware/depthcharge_gdb/depthcharge.elf --directory ~/trunk/src/third_party/coreboot/payloads/libpayload --directory ~/trunk/src/platform/depthcharge --directory ~/trunk/src/platform/vboot_reference --ex "target remote <cpu_uart_pty>"' and behold the magic. (You can also SIGSTOP your terminal's parent shell and the terminal itself, and SIGCONT them in reverse order after GDB exits. More convenient wrapper tools to do all this automatically coming soon.) Original-Change-Id: Ib440d1804126cdfdac4a8801f5015b4487e25269 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202563 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 9c4a642c7be2faf122fef39bdfaddd64aec68b77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9238b4eb19d3ab2c98e4e1c5946cd7d252ca3c3b Reviewed-on: http://review.coreboot.org/8119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 20:57:38 +02:00
config REMOTEGDB
bool "Remote GDB stub"
default n
depends on GPL
help
Enable Remote GDB debugging support.
libpayload: Move MEMMAP_RAM_ONLY to generic options MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 21:14:46 +01:00
config MEMMAP_RAM_ONLY
bool "Only consider RAM entries in memory map for further processing"
default n
libpayload update * rework Config.in * add string_to_args function to actually make getopt usable. * add strchr * add strlcat * some malloc fixes (exposed by the USB stack) * add malloc debugging (thanks to Matthias Krause from Secunet!) * make LAR support optional, it's not really used anymore * (define htoX macros for ppc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 23:15:19 +01:00
endmenu
This change adds PPC support to libpayload, and hooks it up in the build process. The PPC support is still stubbed, with commented out x86 code as guide line for an implementor. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 12:02:52 +02:00
menu "Architecture Options"
choice
prompt "Target Architecture"
Change TARGET_I386 to ARCH_X86 This renames TARGET_I386 to ARCH_X86 to make it more uniform with other parts of the codebase, e.g. cbfs_core.h from cbfstool. Change-Id: I1babcc941245ed1dde0478a21828766759373a42 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1961 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-11-30 22:56:31 +01:00
default ARCH_X86
This change adds PPC support to libpayload, and hooks it up in the build process. The PPC support is still stubbed, with commented out x86 code as guide line for an implementor. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 12:02:52 +02:00
ARM: Generalize armv7 as arm. There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2013-10-01 08:00:33 +02:00
config ARCH_ARM
bool "ARM"
This change adds PPC support to libpayload, and hooks it up in the build process. The PPC support is still stubbed, with commented out x86 code as guide line for an implementor. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 12:02:52 +02:00
help
ARM: Generalize armv7 as arm. There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2013-10-01 08:00:33 +02:00
Support the ARM architecture
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
libpayload: Initial ARMv7 port This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:05:21 +01:00
config ARCH_X86
bool "x86"
help
Support the x86 architecture
libpayload: Add support for arm64 in libpayload Basic support for arm64 is enabled in libpayload. Features added: 1) mem* operations in assembly. 2) Basic exception handling and support for testing exceptions. 3) Caching support. Tested with arm64-generic board compilation. BUG=None BRANCH=None TEST=Compilation successful Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187067 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251 Reviewed-on: http://review.coreboot.org/8063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-02-19 20:35:30 +01:00
config ARCH_ARM64
bool "ARM64"
help
Support the ARM64 architecture
libpayload: Add mock architecture Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-15 14:52:45 +02:00
config ARCH_MOCK
bool "Mock architecture (for unit tests)"
help
This enables the mock architecture (for unit tests) that is intended
to be used for testing purposes, to either test payloads or libpayload itself.
It provides necessary headers, but requires mocking (providing implementation
for) arch-specific functions.
This change adds PPC support to libpayload, and hooks it up in the build process. The PPC support is still stubbed, with commented out x86 code as guide line for an implementor. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 12:02:52 +02:00
endchoice
[PATCH] libpayload: Add multiboot support Make libpayload applications multiboot compatible. Add the multiboot OS table and grok the loader table, especially the memory map and the command line. This makes libpayload applications loadable by GRUB. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 18:51:43 +02:00
config MULTIBOOT
bool "Multiboot header support"
Change TARGET_I386 to ARCH_X86 This renames TARGET_I386 to ARCH_X86 to make it more uniform with other parts of the codebase, e.g. cbfs_core.h from cbfstool. Change-Id: I1babcc941245ed1dde0478a21828766759373a42 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1961 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-11-30 22:56:31 +01:00
depends on ARCH_X86
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if !CHROMEOS
[PATCH] libpayload: Add multiboot support Make libpayload applications multiboot compatible. Add the multiboot OS table and grok the loader table, especially the memory map and the command line. This makes libpayload applications loadable by GRUB. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 18:51:43 +02:00
libpayload: Move base address, stack and heap size to Kconfig This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 01:18:17 +01:00
config HEAP_SIZE
int "Heap size"
default 131072
help
This is the heap size (malloc'able size) available
to the payload.
If unsure, set to 131072 (128K)
config STACK_SIZE
int "Stack size"
default 16384
help
This is the stack size available to the payload.
If unsure, set to 16384 (16K)
config BASE_ADDRESS
hex "Base address"
default 0x04000000 if ARCH_ARM
default 0x80100000 if ARCH_ARM64
default 0x00100000 if ARCH_X86
libpayload: Add mock architecture Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-15 14:52:45 +02:00
default 0x00000000 if ARCH_MOCK
libpayload: Move base address, stack and heap size to Kconfig This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 01:18:17 +01:00
help
This is the base address for the payload.
Remove MIPS architecture The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-17 00:35:39 +02:00
If unsure, set to 0x00100000 on x86,
libpayload: Move base address, stack and heap size to Kconfig This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 01:18:17 +01:00
0x04000000 on ARM or 0x80100000 on ARM64.
[PATCH] libpayload: Add multiboot support Make libpayload applications multiboot compatible. Add the multiboot OS table and grok the loader table, especially the memory map and the command line. This makes libpayload applications loadable by GRUB. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 18:51:43 +02:00
endmenu
libpayload: Enable building libpayload with march=i586 Add a Kconfig value to enable building libpayload with the 586 compiler. Update the cross compiler script to add the Kconfig value name that is used when libpayload builds. The Quark SOC does not support some of the instructions generated with the 686 compiler (e.g. CMOV). Success occurs when payloads/libpayload/build/config.h indicates that CONFIG_LP_USE_MARCH_586=1. TEST=Build and run on Galileo Gen2. Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-20 23:33:28 +02:00
config USE_MARCH_586
bool "Use march=586 qualifier to build"
default n
depends on ARCH_X86
help
Allow a platform or processor to select to be compiled using
the '-march=i586' option instead of the typical '-march=i686'
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
menu "Standard Libraries"
config LIBC
bool "Enable C library support"
default y
libpayload: Add PDCurses and ncurses' libform/libmenu PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-07 15:41:53 +02:00
config CURSES
bool "Build a curses library"
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if !CHROMEOS
libpayload: Add PDCurses and ncurses' libform/libmenu PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-07 15:41:53 +02:00
choice
prompt "Curses implementation"
default PDCURSES
depends on CURSES
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
config TINYCURSES
libpayload/Kconfig: Use official spelling for TinyCurses TinyCursess is officially spelled in CamelCase [1]. [1] https://github.com/tommyettinger/TinyCurses Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11727 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-26 12:30:08 +02:00
bool "TinyCurses"
libpayload: Add PDCurses and ncurses' libform/libmenu PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-07 15:41:53 +02:00
help
libpayload/Kconfig: Use official spelling for TinyCurses TinyCursess is officially spelled in CamelCase [1]. [1] https://github.com/tommyettinger/TinyCurses Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11727 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-26 12:30:08 +02:00
TinyCurses was the first curses implementation for libpayload.
libpayload: Add PDCurses and ncurses' libform/libmenu PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-07 15:41:53 +02:00
It features low memory consumption, static allocation of larger
data structures (so few or no memory allocation calls) and a
reduced feature set.
config PDCURSES
bool "PDCurses"
help
libpayload's PDCurses port provides a full features curses
implementation, including libpanel, libmenu and libform (which
are taken from ncurses).
It requires more system resources, in particularily heap memory.
endchoice
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
libpayload: Implement new CBFS access API This commit adds new CBFS API, which is based on the one available in the main coreboot source tree. Libpayload implementation supports RO/RW file lookups and file contents verification. Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-15 09:36:07 +01:00
source "libcbfs/Kconfig"
libpayload: Add liblzma, libcbfs Add cbfs core from coreboot into libpayload, and to support lzma decode, add coreboot's lzma code, too. Carl-Daniel agreed to relicense the lzmadecode wrapper as BSD-l, solving licensing problems. Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-21 15:43:14 +02:00
config LZMA
bool "LZMA decoder"
default y
help
LZMA decoder implementation, usable eg. by CBFS,
but also externally.
libpayload: Add LZ4 decompression algorithm This patch adds support for the LZ4 decompression algorithm to libpayload. It's what all the cool kids are using for decompression these days and has many interesting advantages over LZMA (and everything else I know of): blazing fast decompression (20(!) times faster than LZMA, twice as fast as LZO on my Cortex-A72), no memory requirements on decompression, and possibly in-place decompression support. It pays for that with a lower compression ratio (about 50% larger compressed size than LZMA, 10% larger than LZO for an ARM64 Linux kernel binary), but the boot time math still works in its favor for our IO speeds. This patch only adds the raw decompression functions for use by external payloads, we can later try integrating them in CBFS. It copies the decompression code itself unmodified from the upstream LZ4 library at github.com/Cyan4973/lz4 which will hopefully make it easy to update. The frame format parsing is reimplemented since the upstream version looks unnecessarily complex and unreadable for our needs. BRANCH=smaug BUG=chrome-os-partner:32184 TEST=With other patches, booted ARM64 kernel that got compressed from 15M to 5.1M and decompresses in 44ms. Change-Id: I65bdc4b2b19bd51c7b7e17a4e4b79da301a2a014 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8a1fc996d5b0234d07f567fa8163d0f802d5144 Original-Change-Id: I15c0620da05561ade2552b15ffdf6bb3afd7eb26 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282743 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 19:30:30 +02:00
config LZ4
bool "LZ4 decoder"
default y
help
Decoder implementation for the LZ4 compression algorithm.
Adds standalone functions (CBFS support coming soon).
libpayload: Enable vboot integration This patch introduces building and linking of 3rdparty/vboot with libpayload. VBoot can be enabled by setting CONFIG_LP_VBOOT_LIB. Moreover it can be configured to use either TPM or TPM 2.0 mode, and whether to use SHA256 processor extension instructions on x86. Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-06 10:01:50 +01:00
source "vboot/Kconfig"
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
endmenu
menu "Console Options"
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
libpayload: Add an option to skip console initialization on startup. A payload may want to decide whether it uses certain input/output consoles, or that it wants support for outputing to a particular device but not to use that device as a console. This change adds a config option which skips the call to console_init in start_main. Change-Id: I32b224d4d0bd3a239b402ecb09ee907d53225735 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1732 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-05 20:43:39 +02:00
config SKIP_CONSOLE_INIT
bool "Skip initializing the consoles at startup"
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if CHROMEOS
libpayload: Add an option to skip console initialization on startup. A payload may want to decide whether it uses certain input/output consoles, or that it wants support for outputing to a particular device but not to use that device as a console. This change adds a config option which skips the call to console_init in start_main. Change-Id: I32b224d4d0bd3a239b402ecb09ee907d53225735 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1732 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-05 20:43:39 +02:00
default n
help
Normally, libpayload will initialize console input/output on startup
before the payload itself gets control. This option disables that
behavior and leaves console initialization up to the payload.
libpayload: Add support for the CBMEM in memory console. Change-Id: I1489b5306ef1ca078686fed4dba2d242f70ad941 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1727 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-29 09:21:27 +02:00
config CBMEM_CONSOLE
bool "Send output to the in memory CBMEM console"
default y
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
config SERIAL_CONSOLE
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
bool "See output on the serial port console"
default y
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE While the 8250 compatible serial port driver is primarily useful on x86 systems because it works with the legacy x86 com ports, some devices which aren't x86 based have 8250 compatible UARTs as well. This change renames the CONFIG_X86_SERIAL_CONSOLE option to the more general and direct CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86 systems can enable the driver, although it will default to on on x86 and off otherwise. Also, the default IO port address that's added to the sysinfo structure on x86 and which is intended to be overwritten by a value in the coreboot tables is not used on ARM. That variable is adjusted so that it's more clear it's a default value, and made dependent on x86 since that's the only place its value is actually used. Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170834 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6655 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-27 01:13:08 +02:00
config 8250_SERIAL_CONSOLE
libpayload: Remove redundant 8250 MMIO32 UART driver The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24 01:18:12 +01:00
bool "8250-compatible serial port driver (including IO and MMIO)"
libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE While the 8250 compatible serial port driver is primarily useful on x86 systems because it works with the legacy x86 com ports, some devices which aren't x86 based have 8250 compatible UARTs as well. This change renames the CONFIG_X86_SERIAL_CONSOLE option to the more general and direct CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86 systems can enable the driver, although it will default to on on x86 and off otherwise. Also, the default IO port address that's added to the sysinfo structure on x86 and which is intended to be overwritten by a value in the coreboot tables is not used on ARM. That variable is adjusted so that it's more clear it's a default value, and made dependent on x86 since that's the only place its value is actually used. Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170834 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6655 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-27 01:13:08 +02:00
depends on SERIAL_CONSOLE
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if ARCH_X86
libpayload: only compile drivers/serial.c on machines that use it. Create a new serial console variable, X86_SERIAL_CONSOLE which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined. Builds for x86 and ARM. Change-Id: I607253c418de015975a839e3c33577842885ec0c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2412 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15 17:13:29 +01:00
libpayload: serial: Move the depthcharge serial drivers into libpayload. These drivers need to be ready right away and never really fit into the depthcharge driver model anyway. CQ-DEPEND=CL:194063 BUG=None TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze, and daisy. BRANCH=None Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194057 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93 Reviewed-on: http://review.coreboot.org/7224 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-04-10 10:07:28 +02:00
config S5P_SERIAL_CONSOLE
bool "Exynos SOC, S5P compatible serial port driver"
depends on SERIAL_CONSOLE
default n
libpayload: ipq808x: introduce uart driver This adds a UART driver for the ipq8064 controller. It still does not quite work in the receive direction - the receive FIFO returns read data in 32 bit chunks, which means that 4 keys need to be pressed before a character pops out of the driver (and it reports it as a single character). This issue is being addressed separately, the driver is being checked in to facilitate concurrent development. BUG=chrome-os-partner:27784, chrome-os-partner:29313 TEST=with deptcharge modifications in place, the AP148 board comes up to the depthcharge prompt: Starting depthcharge on storm... Original-Change-Id: Ief2cfcca73494be5c4147881144470078adcefb8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202045 Original-Reviewed-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 4499318fb9a4e663c504d7c41380ccf2aa89da29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e07d7568c20c0e570222971ff219de3a6d9b7cc Reviewed-on: http://review.coreboot.org/8061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-28 03:28:59 +02:00
config IPQ806X_SERIAL_CONSOLE
bool "IPQ806x SOC compatible serial port driver"
depends on SERIAL_CONSOLE
libpayload: Add drivers for bg4cd BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-09 18:56:43 +02:00
default n
libpayload: ipq40xx: Introduce timer and uart driver BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-01 07:02:12 +01:00
config IPQ40XX_SERIAL_CONSOLE
bool "IPQ40xx SOC compatible serial port driver"
depends on SERIAL_CONSOLE
default n
libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22 08:08:20 +01:00
config QCS405_SERIAL_CONSOLE
bool "QCS405 SOC compatible serial port driver"
depends on SERIAL_CONSOLE
default n
libpayload: Add uart/serial driver support for trogdor Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-10 21:26:15 +02:00
config QUALCOMM_QUPV3_SERIAL_CONSOLE
bool "Qualcomm QUPV3 serial port driver"
depends on SERIAL_CONSOLE
default n
libpayload: Add minimal support for PL011 UART This creates a new PL011 config variable which avoids the infinite busy wait on serial_putchar() because the register mapping is not compatible with current implementation. BUG=None BRANCH=none TEST=printf() works on the PL011 based ARMv8 foundation model Original-Change-Id: I9feda35a50a3488fc504d1561444161e0889deda Original-Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/187020 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 85779a34a161c324cc8af995ada4393137275f20) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: payloads/libpayload/Config.in payloads/libpayload/drivers/serial.c Change-Id: I23c8b3728cd7d2d7692b3e86a679e061e88f7bb5 Reviewed-on: http://review.coreboot.org/7422 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-18 23:17:38 +01:00
config PL011_SERIAL_CONSOLE
bool "PL011 compatible serial port driver"
depends on 8250_SERIAL_CONSOLE
default n
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
config SERIAL_IOBASE
libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE While the 8250 compatible serial port driver is primarily useful on x86 systems because it works with the legacy x86 com ports, some devices which aren't x86 based have 8250 compatible UARTs as well. This change renames the CONFIG_X86_SERIAL_CONSOLE option to the more general and direct CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86 systems can enable the driver, although it will default to on on x86 and off otherwise. Also, the default IO port address that's added to the sysinfo structure on x86 and which is intended to be overwritten by a value in the coreboot tables is not used on ARM. That variable is adjusted so that it's more clear it's a default value, and made dependent on x86 since that's the only place its value is actually used. Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170834 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6655 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-27 01:13:08 +02:00
## This default is currently not used on non-x86 systems.
hex "Default I/O base for the serial port (default 0x3f8)"
depends on SERIAL_CONSOLE && ARCH_X86
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
default 0x3f8
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
config SERIAL_SET_SPEED
bool "Override the serial console baud rate"
default n
Various small consistency fixes (trivial): - Use _FOO_H include guard format everywhere. - Add missing speaker.c prototypes to libpayload.h. - Consistently use short form u8/u16/u32 instead of uint8_t et. al. - kcofig: Use 'depends on' instead of 'depends', which seems deprecated. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 20:01:50 +02:00
depends on SERIAL_CONSOLE
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
config SERIAL_BAUD_RATE
int "Serial console baud rate (default 115200)"
Various small consistency fixes (trivial): - Use _FOO_H include guard format everywhere. - Add missing speaker.c prototypes to libpayload.h. - Consistently use short form u8/u16/u32 instead of uint8_t et. al. - kcofig: Use 'depends on' instead of 'depends', which seems deprecated. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 20:01:50 +02:00
depends on SERIAL_SET_SPEED
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
default 115200
Add a kconfig option to choose between outputing ACS characters or their plain ASCII fallbacks over serial console. Signed-off-by: Ulf Jordan <jordan@chalmers.se> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 21:29:41 +02:00
config SERIAL_ACS_FALLBACK
bool "Use plain ASCII characters for ACS"
default n
depends on SERIAL_CONSOLE
help
The alternate character set (ACS) is used for drawing lines and
displaying a couple of other special graphics characters. The
ACS characters generally look good on screen, but can be difficult
to cut and paste from a terminal window to a text editor.
Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 08:56:47 +02:00
Add a kconfig option to choose between outputing ACS characters or their plain ASCII fallbacks over serial console. Signed-off-by: Ulf Jordan <jordan@chalmers.se> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 21:29:41 +02:00
Say 'y' here if you want to always use plain ASCII characters to
Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 08:56:47 +02:00
approximate the appearance of ACS characters on the serial port
Add a kconfig option to choose between outputing ACS characters or their plain ASCII fallbacks over serial console. Signed-off-by: Ulf Jordan <jordan@chalmers.se> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 21:29:41 +02:00
console.
libpayload: Add video console framework Add a framework for multiple video console drivers. This is to prepare for the Geode driver. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 00:49:02 +02:00
config VIDEO_CONSOLE
bool "See output on a video console"
default y
config VGA_VIDEO_CONSOLE
bool "VGA video console driver"
libpayload: Initial ARMv7 port This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:05:21 +01:00
depends on ARCH_X86 && VIDEO_CONSOLE
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if !CHROMEOS
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
libpayload: Rename Geode video driver to Geode LX video driver. This is simply wrong, the "Geode" video driver is only good for LX and one of our users got bit by this just now. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-08 16:47:41 +02:00
config GEODELX_VIDEO_CONSOLE
bool "Geode LX video console driver"
libpayload: Initial ARMv7 port This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:05:21 +01:00
depends on ARCH_X86 && VIDEO_CONSOLE
libpayload: Add a Geode video driver Add a Geode video driver in lieu of VGA on Geode LX devices Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 17:48:21 +02:00
default n
Add coreboot framebuffer support to libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 19:56:26 +01:00
config COREBOOT_VIDEO_CONSOLE
bool "coreboot video console driver"
depends on VIDEO_CONSOLE && !GEODELX_VIDEO_CONSOLE
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if CHROMEOS
Add coreboot framebuffer support to libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 19:56:26 +01:00
default n
help
Say Y here if coreboot switched to a graphics mode and
your payload wants to use it.
libpayload/corebootfb: Add option to center a 80x25 console This makes payloads which are hardcoded to a 80x25 console look much better, e.g. FILO with its "GRUB" user interface. Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-23 13:23:09 +01:00
config COREBOOT_VIDEO_CENTERED
bool "Center a classic 80x25 console on bigger screens"
depends on COREBOOT_VIDEO_CONSOLE
help
Say 'y' here if your payload is hardcoded to a 80x25 console. Otherwise
its output would look squeezed into the upper-left corner of the screen.
libpayload: video: Add support for font scaling with a factor This introduces support for font scaling with a factor provided via Kconfig. In practice, the font itself is not scaled at any point in memory and only the logic to determine whether a pixel should be filled or not is changed. Thus, it should not significantly impact either the access time or memory use. Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/20709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-23 15:05:47 +02:00
config FONT_SCALE_FACTOR
int "Scale factor for the included font"
depends on GEODELX_VIDEO_CONSOLE || COREBOOT_VIDEO_CONSOLE
default 0
help
By default (value of 0), the scale factor is automatically
calculated to ensure at least 130 columns (when possible).
libpayload: cbgfx: Replace bilinear resampling with Lanczos This patch improves the image resampling (scaling) code in CBGFX to use the Lanczos algorithm that is widely considered the "best" resampling algorithm (e.g. also the first choice in Python's PIL library). It is of course much more elaborate and therefore slower than bilinear resampling, but a lot of the difference can be made up with optimizations, and the resulting code was found to still produce acceptable speeds for existing Chrome OS UI use cases (on an Arm Cortex-A55 device, time to scale an image to 1101x593 went from ~88ms to ~275ms, a little over 3x slowdown). Nevertheless, if this should be too slow for anyone there's also an option to tune it down a little, but still much better than bilinear (same operation was ~170ms with this). Example images (scaled up by a factor of 7): Old (bilinear): https://i.imgur.com/ytr2n4Z.png New (Lanczos a=3): https://i.imgur.com/f0vKluM.png Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-06-25 04:43:36 +02:00
config CBGFX_FAST_RESAMPLE
bool "CBGFX: use faster (less pretty) image scaling"
default n
help
When payloads use the CBGFX library to draw .BMPs on the screen,
they will be resampled with an anti-aliasing filter to scale to the
requested output size. The default implementation should normally be
fast enough, but if desired this option can make it about 50-100%
faster at the cost of quality. (It changes the 'a' parameter in the
Lanczos resampling algorithm from 3 to 2.)
Only affects .BMPs that aren't already provided at the right size.
libpayload-x86: Add common i8042 driver Add a common i8042 driver that uses multiple overflowing fifos to seperate PS/2 port and PS/2 aux port. Required to support PC keyboard and PC mouse at the same time. Tested on Lenovo T500. Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18594 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-03-01 19:07:37 +01:00
config PC_I8042
bool "A common PC i8042 driver"
libpayload-x86: Add PS2 mouse driver Make use of i8042 driver to add PS2 mouse driver support. Tested on Lenovot T500. The touchpad can be used to drive the mouse cursor. Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-02-06 15:26:58 +01:00
default y if PC_KEYBOARD || PC_MOUSE
libpayload-x86: Add common i8042 driver Add a common i8042 driver that uses multiple overflowing fifos to seperate PS/2 port and PS/2 aux port. Required to support PC keyboard and PC mouse at the same time. Tested on Lenovo T500. Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18594 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-03-01 19:07:37 +01:00
default n
help
To be used by PC_KEYBOARD and PC_MOUSE.
libpayload-x86: Add PS2 mouse driver Make use of i8042 driver to add PS2 mouse driver support. Tested on Lenovot T500. The touchpad can be used to drive the mouse cursor. Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-02-06 15:26:58 +01:00
config PC_MOUSE
bool "Allow input from a PC mouse"
libpayload: disable mouse on CHROMEOS We already have that Kconfig flag, so I guess we should use it for consistency. Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-17 17:57:14 +02:00
default n if CHROMEOS
libpayload-x86: Add PS2 mouse driver Make use of i8042 driver to add PS2 mouse driver support. Tested on Lenovot T500. The touchpad can be used to drive the mouse cursor. Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-02-06 15:26:58 +01:00
default y if ARCH_X86 # uses IO
default n
help
PS/2 mouse driver on top of PC_I8042.
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
config PC_KEYBOARD
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
bool "Allow input from a PC keyboard"
libpayload: Remove PC Keyboard from ARM build The keyboard.c uses IO cycles to access the legacy PC keyboard device. ARM can't do IO cycles, so remove the option for ARM configs. Change-Id: Ifc6c2368563f27867f4babad5afdde0e78f4cf78 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7922 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-23 23:22:30 +01:00
default y if ARCH_X86 # uses IO
default n
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
* add keyboard layout support to libpayload * add a reset handler mechanism (CTRL-ALT-DEL) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 20:37:26 +02:00
config PC_KEYBOARD_LAYOUT_US
bool "English (US) keyboard layout"
depends on PC_KEYBOARD
default y
config PC_KEYBOARD_LAYOUT_DE
bool "German keyboard layout"
depends on PC_KEYBOARD
default n
libpayload: i8042: Enable keyboard translation by default on exit Add a Kconfig option to set the keyboard translation state on exit and set the default to true. This restores the keyboard to the power-up defaults for firmware that does not always run libpayload keyboard init to have consistent state, and provides an option to disable translation for keyboards that might need it. Change-Id: I25dfe3f425a5bb57e97476564886672b707aa3bd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28 18:40:26 +02:00
config PC_KEYBOARD_TRANSLATION
bool "Enable or Disable translation in PC keyboard set 2 on exit"
depends on PC_KEYBOARD
default y
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
endmenu
menu "Drivers"
config PCI
bool "Support for PCI devices"
libpayload/pci: Add support for bus mapping Move the common APIs to pci_ops.c and IO based operations to pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-28 10:44:43 +02:00
default y if ARCH_X86
default n
config PCI_IO_OPS
bool "Support for PCI devices with port IO"
depends on PCI && IO_ADDRESS_SPACE
default y if ARCH_X86
default n
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
libpayload/pci: Add pci_map_bus function for MediaTek platform Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-28 10:53:43 +02:00
config PCIE_MEDIATEK
bool "Support for PCIe devices on MediaTek platforms"
depends on PCI && !PCI_IO_OPS
default n
libpayload/pci: Add pci_map_bus function for Qualcomm platform Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 03:23:37 +02:00
config PCIE_QCOM
bool "Support for PCIe devices on Qualcomm platforms"
depends on PCI && !PCI_IO_OPS
default n
Due to popular demand, rename "CMOS" to "NVRAM" (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:17:39 +02:00
config NVRAM
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
bool "Support for reading/writing NVRAM bytes"
libpayload: Initial ARMv7 port This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:05:21 +01:00
depends on ARCH_X86 # for now
Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 17:21:24 +02:00
default y
Add initial support for some basic CMOS read/write functions and the bcd2dec()/dec2bcd() functions we'll need for (among other things) converting some date/time parameters in CMOS. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-28 00:26:40 +01:00
libpayload: Add mouse cursor driver Add a driver to handle multiple low level mouse drivers and provide basic cursor acceleration support. Tested on Lenovo T500. Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-02-06 15:02:25 +01:00
config MOUSE_CURSOR
bool "Support for mouse cursor handling"
libpayload-x86: Add PS2 mouse driver Make use of i8042 driver to add PS2 mouse driver support. Tested on Lenovot T500. The touchpad can be used to drive the mouse cursor. Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-02-06 15:26:58 +01:00
default y if PC_MOUSE
libpayload: Add mouse cursor driver Add a driver to handle multiple low level mouse drivers and provide basic cursor acceleration support. Tested on Lenovo T500. Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-02-06 15:02:25 +01:00
default n
help
Provides a common interface for various mouse cursor drivers.
* Supports up to 32 buttons.
* Supports 3 axis mice.
* Applies simple cursor acceleration.
* Allows to set cursor acceleration and cursor speed.
Fix the NVRAM access functions to work correctly for the upper 128 bytes of NVRAM (if enabled). For most chipsets this means using I/O ports 0x72/0x73, but at least on some VIA chipsets (I tested the VIA VT8237R on actual hardware) these ports won't work and you have to use 0x74/0x75. Thus, make this a Kconfig option for now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 22:21:49 +02:00
config RTC_PORT_EXTENDED_VIA
bool "Extended RTC ports are 0x74/0x75"
default n
help
For recent chipsets with 256 NVRAM bytes, you have to access the
upper 128 bytes (128-255) using two different I/O ports,
usually 0x72/0x73.
Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 08:56:47 +02:00
Fix the NVRAM access functions to work correctly for the upper 128 bytes of NVRAM (if enabled). For most chipsets this means using I/O ports 0x72/0x73, but at least on some VIA chipsets (I tested the VIA VT8237R on actual hardware) these ports won't work and you have to use 0x74/0x75. Thus, make this a Kconfig option for now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 22:21:49 +02:00
On some chipsets this can be a different set of ports, though.
The VIA VT8237R for example only recognizes the ports 0x74/0x75
for accessing the high 128 NVRAM bytes (as seems to be the case for
multiple VIA chipsets).
Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 08:56:47 +02:00
Fix the NVRAM access functions to work correctly for the upper 128 bytes of NVRAM (if enabled). For most chipsets this means using I/O ports 0x72/0x73, but at least on some VIA chipsets (I tested the VIA VT8237R on actual hardware) these ports won't work and you have to use 0x74/0x75. Thus, make this a Kconfig option for now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 22:21:49 +02:00
If you want to read or write CMOS bytes on computers with one of
these chipsets, say 'y' here.
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
config SPEAKER
bool "Support for PC speaker"
libpayload: Initial ARMv7 port This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14 22:05:21 +01:00
depends on ARCH_X86
libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-17 01:37:56 +02:00
default y if !CHROMEOS
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
libpayload: split "Drivers" config section in Kconfig Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15914 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-27 12:41:04 +02:00
source "drivers/timer/Kconfig"
source "drivers/storage/Kconfig"
source "drivers/usb/Kconfig"
libpayload: add UDC driver for Designware controller Found in rockchips rk3288 as used in google/veyron. BUG=None TEST=None BRANCH=None Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1 Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272108 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-20 11:27:10 +02:00
libpayload update * rework Config.in * add string_to_args function to actually make getopt usable. * add strchr * add strlcat * some malloc fixes (exposed by the USB stack) * add malloc debugging (thanks to Matthias Krause from Secunet!) * make LAR support optional, it's not really used anymore * (define htoX macros for ppc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 23:15:19 +01:00
endmenu
menu "Debugging"
depends on DEVELOPER
config DEBUG_MALLOC
bool "Debug memory allocator"
default n
help
Select this option if you want to debug the memory allocator. This
option logs all uses of the following functions:
void free(void *ptr);
void *malloc(size_t size);
void *calloc(size_t nmemb, size_t size);
void *realloc(void *ptr, size_t size);
void *memalign(size_t align, size_t size);
This patch adds USB capabilities to libpayload. It requires some memalign implementation (eg. the one I sent yesterday). Features: - UHCI controller driver - UHCI root hub driver - USB MSC (Mass Storage Class) driver - skeleton of a USB HID driver (requires better interrupt transfer handling, which is TODO) - skeleton of a USB hub driver (needs several blank spots filled in, eg. power management. Again: TODO) OHCI and EHCI are not supported, though OHCI support should be rather easy as the stack provides reasonable abstractions (or so I hope). EHCI will probably be more complicated. Isochronous transfers (eg. webcams, audio stuff, ...) are not supported. They can be, but I doubt we'll have a reason for that in the boot environment. The MSC driver was tested against a couple of USB flash drives, and should be reasonably tolerant by now. But I probably underestimate the amount of bugs present in USB flash drives, so feedback is welcome. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 18:06:22 +02:00
libpayload update * rework Config.in * add string_to_args function to actually make getopt usable. * add strchr * add strlcat * some malloc fixes (exposed by the USB stack) * add malloc debugging (thanks to Matthias Krause from Secunet!) * make LAR support optional, it's not really used anymore * (define htoX macros for ppc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-25 23:15:19 +01:00
Say N here unless you are debugging memory allocator problems.
This patch adds USB capabilities to libpayload. It requires some memalign implementation (eg. the one I sent yesterday). Features: - UHCI controller driver - UHCI root hub driver - USB MSC (Mass Storage Class) driver - skeleton of a USB HID driver (requires better interrupt transfer handling, which is TODO) - skeleton of a USB hub driver (needs several blank spots filled in, eg. power management. Again: TODO) OHCI and EHCI are not supported, though OHCI support should be rather easy as the stack provides reasonable abstractions (or so I hope). EHCI will probably be more complicated. Isochronous transfers (eg. webcams, audio stuff, ...) are not supported. They can be, but I doubt we'll have a reason for that in the boot environment. The MSC driver was tested against a couple of USB flash drives, and should be reasonably tolerant by now. But I probably underestimate the amount of bugs present in USB flash drives, so feedback is welcome. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 18:06:22 +02:00
libpayload: The initial chunk of code writen by AMD This is the initial chunk of code written by me and copyrighted by AMD. Includes everything but a few files that we pulled from outside sources. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:56:58 +01:00
endmenu
new menu structure for libpayload Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 15:45:03 +02:00
Refactor the endianness conversion functions and header files. The endianness of an architecture is now set up automatically using Kconfig and some common code. The available conversion functions were also expanded to go to or from a particular endianness. Those use the abbreviation le or be for little or big endian. Built for Stumpy and saw coreinfo cbfs support work which uses network byte order. Used the functions which convert to little endian to implement an AHCI driver. The source arch is also little endian, so they were effectively (and successfully) inert. Change-Id: I3a2d2403855b3e0e93fa34f45e8e542b3e5afeac Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1719 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-19 11:06:46 +01:00
config BIG_ENDIAN
default n
bool
config LITTLE_ENDIAN
default n
bool
libpayload: Make whether or not there's an IO address space configurable Default it to no to be consistent with the other architecture wide options (endianness), and turn it on explicitly for x86 and PowerPC. Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2658 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-19 00:49:00 +01:00
config IO_ADDRESS_SPACE
default n
bool
libpayload: Make comment into help text Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 20:48:44 +01:00
help
This option is turned on if the target system has a separate
IO address space. This is typically only the case on x86.
libpayload: Make whether or not there's an IO address space configurable Default it to no to be consistent with the other architecture wide options (endianness), and turn it on explicitly for x86 and PowerPC. Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2658 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-19 00:49:00 +01:00
libpayload: Rename Config.in -> Kconfig libpayload is the only Kconfig based project under the coreboot umbrella that is using Config.in as its name for Kconfig config files. Rename that to Kconfig as on the other projects for consistency. Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-11 23:33:11 +02:00
source "arch/arm/Kconfig"
source "arch/arm64/Kconfig"
source "arch/x86/Kconfig"
libpayload: Add mock architecture Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-15 14:52:45 +02:00
source "arch/mock/Kconfig"