42 lines
1.3 KiB
ArmAsm
42 lines
1.3 KiB
ArmAsm
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* This code is compiled for both arm64 and arm4, however the code is only
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* executed by the armv8 cores coming out of reset.
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*/
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#if !defined(__PRE_RAM__)
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#define INST .inst
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#else
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#define INST .word
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#endif
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/*
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* The Denver cores come up in aarch32 mode. In order to transition to
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* 64-bit mode a write to the RMR (reest mangement register) with the
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* AA64 bit (0) set while setting RR (reset request bit 1).
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*/
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.align 6
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.global reset_entry_32bit
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reset_entry_32bit:
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INST 0xe3a00003 /* mov r0, #3 */
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INST 0xee0c0f50 /* mcr 15, 0, r0, cr12, cr0, {2} */
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INST 0xeafffffe /* b . */
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