coreboot-kgpe-d16/src/soc/amd/picasso/bootblock.c

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/tsc.h>
#include <soc/psp_transfer.h>
#include <soc/southbridge.h>
#include <amdblocks/amd_pci_mmconf.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
early_cache_setup();
soc/amd/picasso/bootblock: Write EIP to secure S3 This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-05 00:42:50 +02:00
write_resume_eip();
enable_pci_mmconf();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
* when we use micro-seconds granularity for Zork
*/
base_timestamp /= tsc_freq_mhz();
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
boot_with_psp_timestamp(base_timestamp);
/*
* if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or
* previous step did nothing, proceed with normal bootblock main.
*/
bootblock_main_with_basetime(base_timestamp);
}
void bootblock_soc_early_init(void)
{
fch_pre_init();
}
void bootblock_soc_init(void)
{
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
verify_psp_transfer_buf();
show_psp_transfer_info();
}
fch_early_init();
}