2020-04-04 18:50:57 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2019-04-22 22:55:16 +02:00
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <amdblocks/sata.h>
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#include <soc/southbridge.h>
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void soc_enable_sata_features(struct device *dev)
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{
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u8 *ahci_ptr;
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u32 misc_ctl, cap_cfg;
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u32 temp;
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/* unlock the write-protect */
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misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
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misc_ctl |= SATA_MISC_SUBCLASS_WREN;
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pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
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/* set the SATA AHCI mode to allow port expanders */
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ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
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pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
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cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
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cap_cfg |= SATA_CAPABILITY_SPM;
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write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
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/* lock the write-protect */
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temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
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temp &= ~SATA_MISC_SUBCLASS_WREN;
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pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
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};
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