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coreboot-kgpe-d16/spd/lp5/memory_parts.json

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spd: Add lp5 directory with empty memory_parts file Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 23:55:07 +01:00
{
spd: Add new LP5 parts and generate SPDs Add the parts below which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. Micron MT62F512M32D2DR-031 WT:B Micron MT62F1G32D4DR-031 WT:B Hynix H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 23:49:01 +01:00
"parts": [
{
"name": "MT62F512M32D2DR-031 WT:B",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
},
{
"name": "MT62F1G32D4DR-031 WT:B",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 4,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
"speedMbps": 6400
}
},
{
"name": "H9JCNNNCP3MLYR-N6E",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 4,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
"speedMbps": 6400
}
spd: Add new LP5 part Samsung K3LKBKB0BM-MGCP Samsung K3LKBKB0BM-MGCP will be used by the nissa variant nereid. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:197479026 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I4db983d5015a4dacad0bd03cf7a85f6214856a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-28 07:50:21 +01:00
},
{
"name": "K3LKBKB0BM-MGCP",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
spd/lp5: Add new part H9JCNNNBK3MLYR-N6E Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-13 23:57:37 +01:00
},
{
"name": "H9JCNNNBK3MLYR-N6E",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
spd/lp5: Add new part MT62F2G32D8DR-031 Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 16:50:39 +01:00
},
{
"name": "MT62F2G32D8DR-031 WT:B",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 8,
"bitWidthPerChannel": 8,
"ranksPerChannel": 2,
"speedMbps": 6400
}
spd: Add new LP5 part Samsung K3LKLKL0EM-MGCN Samsung K3LKLKL0EM-MGCN will be used by the nissa variant craask. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:229938024 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5648f297130eaf8541d99b2db7777774a0b1d8fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-17 13:46:03 +02:00
},
{
"name": "K3LKLKL0EM-MGCN",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 5500
}
spd/lp5: Add new LP5 part H58G56AK6BX069 Hynix H58G56AK6BX069 will be used by the brya variant crota. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:233830713 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6136e17706c6248598886f8f9bd8fdd7efff4dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-01 03:35:57 +02:00
},
{
"name": "H58G56AK6BX069",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
spd/lp5: Add SPD for Micron MT62F1G32D4DS This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-01 04:55:28 +02:00
},
{
"name": "MT62F1G32D4DS-031 WT:B",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 4,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
"speedMbps": 6400
}
spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCP This adds support for Samsung K3LKCKC0BM-MGCP LP5 chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=None BUG=235664831 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I49cea0594f8a94aa7efbb375ea1c28b5d1136498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-10 10:47:09 +02:00
},
{
"name": "K3LKCKC0BM-MGCP",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 4,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
"speedMbps": 6400
}
spd/lp5: Add support for MT62F1G32D2DS-026 WT:B Datasheet is available in the bug. BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Iadd4bf07d38dbd2e1f47df5024282b04dec3c805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65795 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-12 20:38:37 +02:00
},
{
"name": "MT62F1G32D2DS-026 WT:B",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
util/spd_tools: Add support for LP5X SPDs This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-23 22:14:16 +02:00
"speedMbps": 7500,
"lp5x": true
spd/lp5: Add support for MT62F1G32D2DS-026 WT:B Datasheet is available in the bug. BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Iadd4bf07d38dbd2e1f47df5024282b04dec3c805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65795 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-12 20:38:37 +02:00
}
spd/lp5: Add SPD for Micron MT62F2G32D4DS-026 This adds support for Micron MT62F2G32D4DS-026 chips. BUG=b:240289148 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1212506d742178803a7e7bf7e0236d1095f7af9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-26 22:49:44 +02:00
},
{
"name": "MT62F2G32D4DS-026 WT:B",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 4,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
util/spd_tools: Add support for LP5X SPDs This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-23 22:14:16 +02:00
"speedMbps": 7500,
"lp5x": true
spd/lp5: Add SPD for Micron MT62F2G32D4DS-026 This adds support for Micron MT62F2G32D4DS-026 chips. BUG=b:240289148 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1212506d742178803a7e7bf7e0236d1095f7af9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-26 22:49:44 +02:00
}
spd: Add new LP5 parts and generate SPDs Add the parts below which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. Micron MT62F512M32D2DR-031 WT:B Micron MT62F1G32D4DR-031 WT:B Hynix H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 23:49:01 +01:00
}
]
spd: Add lp5 directory with empty memory_parts file Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 23:55:07 +01:00
}