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coreboot-kgpe-d16/util/inteltool/gpio_groups.c

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inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
* Copyright (C) 2017 secunet Security Networks AG
inteltool: add Lewisburg C62x GPIOs support These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-17 13:54:02 +02:00
* Copyright (C) 2019 YADRO
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <stdint.h>
#include <assert.h>
#include <inttypes.h>
#include "inteltool.h"
#include "pcr.h"
util/inteltool: Move Apollo Lake definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Apollo Lake definitions into its own header. Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:20:23 +01:00
#include "gpio_names/apollolake.h"
util/inteltool: Move Cannon Lake definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Cannon Lake definitions into its own header. Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:16:06 +01:00
#include "gpio_names/cannonlake.h"
util/inteltool: Move Ice Lake definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Ice Lake definitions into its own header. Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:14:18 +01:00
#include "gpio_names/icelake.h"
util/inteltool: Move Lewisburg definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Lewisburg definitions into its own header. Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:29:39 +01:00
#include "gpio_names/lewisburg.h"
util/inteltool: Move Sunrise Point (LP) definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Sunrise Point and Sunrise Point LP definitions into its own header. Change-Id: I06efbee700f1525770365428fb85ef700ac53b80 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:25:45 +01:00
#include "gpio_names/sunrise.h"
util/inteltool: Move Ice Lake definitions into their own header So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Ice Lake definitions into its own header. Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29 09:14:18 +01:00
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
util/inteltool: Add support for Denverton Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-12 19:20:50 +01:00
static const char *const denverton_group_north_all_names[] = {
"NORTH_ALL_GBE0_SDP0",
"NORTH_ALL_GBE1_SDP0",
"NORTH_ALL_GBE0_SDP1",
"NORTH_ALL_GBE1_SDP1",
"NORTH_ALL_GBE0_SDP2",
"NORTH_ALL_GBE1_SDP2",
"NORTH_ALL_GBE0_SDP3",
"NORTH_ALL_GBE1_SDP3",
"NORTH_ALL_GBE2_LED0",
"NORTH_ALL_GBE2_LED1",
"NORTH_ALL_GBE0_I2C_CLK",
"NORTH_ALL_GBE0_I2C_DATA",
"NORTH_ALL_GBE1_I2C_CLK",
"NORTH_ALL_GBE1_I2C_DATA",
"NORTH_ALL_NCSI_RXD0",
"NORTH_ALL_NCSI_CLK_IN",
"NORTH_ALL_NCSI_RXD1",
"NORTH_ALL_NCSI_CRS_DV",
"NORTH_ALL_NCSI_ARB_IN",
"NORTH_ALL_NCSI_TX_EN",
"NORTH_ALL_NCSI_TXD0",
"NORTH_ALL_NCSI_TXD1",
"NORTH_ALL_NCSI_ARB_OUT",
"NORTH_ALL_GBE0_LED0",
"NORTH_ALL_GBE0_LED1",
"NORTH_ALL_GBE1_LED0",
"NORTH_ALL_GBE1_LED1",
"NORTH_ALL_GPIO_0",
"NORTH_ALL_PCIE_CLKREQ0_N",
"NORTH_ALL_PCIE_CLKREQ1_N",
"NORTH_ALL_PCIE_CLKREQ2_N",
"NORTH_ALL_PCIE_CLKREQ3_N",
"NORTH_ALL_PCIE_CLKREQ4_N",
"NORTH_ALL_GPIO_1",
"NORTH_ALL_GPIO_2",
"NORTH_ALL_SVID_ALERT_N",
"NORTH_ALL_SVID_DATA",
"NORTH_ALL_SVID_CLK",
"NORTH_ALL_THERMTRIP_N",
"NORTH_ALL_PROCHOT_N",
"NORTH_ALL_MEMHOT_N",
};
static const struct gpio_group denverton_group_north_all = {
.display = "------- GPIO Group North All -------",
.pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
.func_count = 1,
.pad_names = denverton_group_north_all_names,
};
static const struct gpio_group *const denverton_community_north_groups[] = {
&denverton_group_north_all,
};
static const struct gpio_community denverton_community_north = {
.name = "------- GPIO Community 0 -------",
.pcr_port_id = 0xc2,
.group_count = ARRAY_SIZE(denverton_community_north_groups),
.groups = denverton_community_north_groups,
};
static const char *const denverton_group_south_dfx_names[] = {
"SOUTH_DFX_DFX_PORT_CLK0",
"SOUTH_DFX_DFX_PORT_CLK1",
"SOUTH_DFX_DFX_PORT0",
"SOUTH_DFX_DFX_PORT1",
"SOUTH_DFX_DFX_PORT2",
"SOUTH_DFX_DFX_PORT3",
"SOUTH_DFX_DFX_PORT4",
"SOUTH_DFX_DFX_PORT5",
"SOUTH_DFX_DFX_PORT6",
"SOUTH_DFX_DFX_PORT7",
"SOUTH_DFX_DFX_PORT8",
"SOUTH_DFX_DFX_PORT9",
"SOUTH_DFX_DFX_PORT10",
"SOUTH_DFX_DFX_PORT11",
"SOUTH_DFX_DFX_PORT12",
"SOUTH_DFX_DFX_PORT13",
"SOUTH_DFX_DFX_PORT14",
"SOUTH_DFX_DFX_PORT15",
};
static const struct gpio_group denverton_group_south_dfx = {
.display = "------- GPIO Group South DFX -------",
.pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
.func_count = 1,
.pad_names = denverton_group_south_dfx_names,
};
static const char *const denverton_group_south_group0_names[] = {
"SOUTH_GROUP0_GPIO_12",
"SOUTH_GROUP0_SMB5_GBE_ALRT_N",
"SOUTH_GROUP0_PCIE_CLKREQ5_N",
"SOUTH_GROUP0_PCIE_CLKREQ6_N",
"SOUTH_GROUP0_PCIE_CLKREQ7_N",
"SOUTH_GROUP0_UART0_RXD",
"SOUTH_GROUP0_UART0_TXD",
"SOUTH_GROUP0_SMB5_GBE_CLK",
"SOUTH_GROUP0_SMB5_GBE_DATA",
"SOUTH_GROUP0_ERROR2_N",
"SOUTH_GROUP0_ERROR1_N",
"SOUTH_GROUP0_ERROR0_N",
"SOUTH_GROUP0_IERR_N",
"SOUTH_GROUP0_MCERR_N",
"SOUTH_GROUP0_SMB0_LEG_CLK",
"SOUTH_GROUP0_SMB0_LEG_DATA",
"SOUTH_GROUP0_SMB0_LEG_ALRT_N",
"SOUTH_GROUP0_SMB1_HOST_DATA",
"SOUTH_GROUP0_SMB1_HOST_CLK",
"SOUTH_GROUP0_SMB2_PECI_DATA",
"SOUTH_GROUP0_SMB2_PECI_CLK",
"SOUTH_GROUP0_SMB4_CSME0_DATA",
"SOUTH_GROUP0_SMB4_CSME0_CLK",
"SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
"SOUTH_GROUP0_USB_OC0_N",
"SOUTH_GROUP0_FLEX_CLK_SE0",
"SOUTH_GROUP0_FLEX_CLK_SE1",
"SOUTH_GROUP0_GPIO_4",
"SOUTH_GROUP0_GPIO_5",
"SOUTH_GROUP0_GPIO_6",
"SOUTH_GROUP0_GPIO_7",
"SOUTH_GROUP0_SATA0_LED_N",
"SOUTH_GROUP0_SATA1_LED_N",
"SOUTH_GROUP0_SATA_PDETECT0",
"SOUTH_GROUP0_SATA_PDETECT1",
"SOUTH_GROUP0_SATA0_SDOUT",
"SOUTH_GROUP0_SATA1_SDOUT",
"SOUTH_GROUP0_UART1_RXD",
"SOUTH_GROUP0_UART1_TXD",
"SOUTH_GROUP0_GPIO_8",
"SOUTH_GROUP0_GPIO_9",
"SOUTH_GROUP0_TCK",
"SOUTH_GROUP0_TRST_N",
"SOUTH_GROUP0_TMS",
"SOUTH_GROUP0_TDI",
"SOUTH_GROUP0_TDO",
"SOUTH_GROUP0_CX_PRDY_N",
"SOUTH_GROUP0_CX_PREQ_N",
"SOUTH_GROUP0_CTBTRIGINOUT",
"SOUTH_GROUP0_CTBTRIGOUT",
"SOUTH_GROUP0_DFX_SPARE2",
"SOUTH_GROUP0_DFX_SPARE3",
"SOUTH_GROUP0_DFX_SPARE4",
};
static const struct gpio_group denverton_group_south_group0 = {
.display = "------- GPIO Group South Group0 -------",
.pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
.func_count = 1,
.pad_names = denverton_group_south_group0_names,
};
static const char *const denverton_group_south_group1_names[] = {
"SOUTH_GROUP1_SUSPWRDNACK",
"SOUTH_GROUP1_PMU_SUSCLK",
"SOUTH_GROUP1_ADR_TRIGGER",
"SOUTH_GROUP1_PMU_SLP_S45_N",
"SOUTH_GROUP1_PMU_SLP_S3_N",
"SOUTH_GROUP1_PMU_WAKE_N",
"SOUTH_GROUP1_PMU_PWRBTN_N",
"SOUTH_GROUP1_PMU_RESETBUTTON_N",
"SOUTH_GROUP1_PMU_PLTRST_N",
"SOUTH_GROUP1_SUS_STAT_N",
"SOUTH_GROUP1_SLP_S0IX_N",
"SOUTH_GROUP1_SPI_CS0_N",
"SOUTH_GROUP1_SPI_CS1_N",
"SOUTH_GROUP1_SPI_MOSI_IO0",
"SOUTH_GROUP1_SPI_MISO_IO1",
"SOUTH_GROUP1_SPI_IO2",
"SOUTH_GROUP1_SPI_IO3",
"SOUTH_GROUP1_SPI_CLK",
"SOUTH_GROUP1_SPI_CLK_LOOPBK",
"SOUTH_GROUP1_ESPI_IO0",
"SOUTH_GROUP1_ESPI_IO1",
"SOUTH_GROUP1_ESPI_IO2",
"SOUTH_GROUP1_ESPI_IO3",
"SOUTH_GROUP1_ESPI_CS0_N",
"SOUTH_GROUP1_ESPI_CLK",
"SOUTH_GROUP1_ESPI_RST_N",
"SOUTH_GROUP1_ESPI_ALRT0_N",
"SOUTH_GROUP1_GPIO_10",
"SOUTH_GROUP1_GPIO_11",
"SOUTH_GROUP1_ESPI_CLK_LOOPBK",
"SOUTH_GROUP1_EMMC_CMD",
"SOUTH_GROUP1_EMMC_STROBE",
"SOUTH_GROUP1_EMMC_CLK",
"SOUTH_GROUP1_EMMC_D0",
"SOUTH_GROUP1_EMMC_D1",
"SOUTH_GROUP1_EMMC_D2",
"SOUTH_GROUP1_EMMC_D3",
"SOUTH_GROUP1_EMMC_D4",
"SOUTH_GROUP1_EMMC_D5",
"SOUTH_GROUP1_EMMC_D6",
"SOUTH_GROUP1_EMMC_D7",
"SOUTH_GROUP1_GPIO_3",
};
static const struct gpio_group denverton_group_south_group1 = {
.display = "------- GPIO Group South Group1 -------",
.pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
.func_count = 1,
.pad_names = denverton_group_south_group1_names,
};
static const struct gpio_group *const denverton_community_south_groups[] = {
&denverton_group_south_dfx,
&denverton_group_south_group0,
&denverton_group_south_group1,
};
static const struct gpio_community denverton_community_south = {
.name = "------- GPIO Community 1 -------",
.pcr_port_id = 0xc5,
.group_count = ARRAY_SIZE(denverton_community_south_groups),
.groups = denverton_community_south_groups,
};
static const struct gpio_community *const denverton_communities[] = {
&denverton_community_north, &denverton_community_south,
};
util/inteltool: Add support for Sunrise Point LP Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-24 06:09:47 +02:00
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0)
{
const size_t pad_mode = dw0 >> 10 & 7;
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
const char *const pad_name =
group->pad_names[pad * group->func_count + pad_mode];
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
if (!pad_mode)
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
return pad_name[0] == '*' ? "*GPIO" : "GPIO";
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
else if (pad_mode < group->func_count)
return group->pad_names[pad * group->func_count + pad_mode];
else
return "RESERVED";
}
static void print_gpio_group(const uint8_t pid, size_t pad_cfg,
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
const struct gpio_group *const group,
size_t pad_stepping)
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
{
size_t p;
printf("%s\n", group->display);
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) {
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
const uint32_t dw0 = read_pcr32(pid, pad_cfg);
const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
const char *const pad_name =
group->pad_names[p * group->func_count];
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg,
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
(uint64_t)dw1 << 32 | dw0,
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
pad_name[0] == '*' ? &pad_name[1] : pad_name,
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
decode_pad_mode(group, p, dw0));
}
}
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
static void print_gpio_community(const struct gpio_community *const community,
size_t pad_stepping)
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
{
size_t group, pad_count;
size_t pad_cfg; /* offset in bytes under this communities PCR port */
printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
community->name, (size_t)community->pcr_port_id << 16);
for (group = 0, pad_count = 0; group < community->group_count; ++group)
pad_count += community->groups[group]->pad_count;
assert(pad_count * 8 <= PCR_PORT_SIZE - 0x10);
pad_cfg = read_pcr32(community->pcr_port_id, 0x0c);
if (pad_cfg + pad_count * 8 > PCR_PORT_SIZE) {
fprintf(stderr, "Bad Pad Base Address: 0x%08zx\n", pad_cfg);
return;
}
for (group = 0; group < community->group_count; ++group) {
print_gpio_group(community->pcr_port_id,
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
pad_cfg, community->groups[group],
pad_stepping);
pad_cfg += community->groups[group]->pad_count * pad_stepping;
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
}
}
void print_gpio_groups(struct pci_dev *const sb)
{
size_t community_count;
const struct gpio_community *const *communities;
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
size_t pad_stepping = 8;
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
switch (sb->device_id) {
util/inteltool: Add H110 GPIO support Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28 19:09:08 +02:00
case PCI_DEVICE_ID_INTEL_H110:
inteltool: Add GPIO support for Skylake-H chipsets PCH IDs: - H170, Z170, Q170, Q150, C232, QM170, HM170 Used documents: - Intel 332690-005EN Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-29 21:53:14 +02:00
case PCI_DEVICE_ID_INTEL_H170:
case PCI_DEVICE_ID_INTEL_Z170:
case PCI_DEVICE_ID_INTEL_Q170:
case PCI_DEVICE_ID_INTEL_Q150:
inteltool: Add some Skylake desktop ids Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03 16:03:07 +02:00
case PCI_DEVICE_ID_INTEL_B150:
util/inteltool: Add Kabylake E3-1200 Support Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 17:50:57 +02:00
case PCI_DEVICE_ID_INTEL_C236:
inteltool: Add GPIO support for Skylake-H chipsets PCH IDs: - H170, Z170, Q170, Q150, C232, QM170, HM170 Used documents: - Intel 332690-005EN Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-29 21:53:14 +02:00
case PCI_DEVICE_ID_INTEL_C232:
case PCI_DEVICE_ID_INTEL_QM170:
case PCI_DEVICE_ID_INTEL_HM170:
case PCI_DEVICE_ID_INTEL_CM236:
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
community_count = ARRAY_SIZE(sunrise_communities);
communities = sunrise_communities;
pcr_init(sb);
break;
inteltool: Add Sunrise Point-LP Skylake PCH IDs Sunrise Point-LP is used on Skylake and KabyLake platforms, but the PCH IDs differ. This commit adds the PCH IDs for Skylake mobile platforms and renames the Kabylake macros to distinguish them. Used Intel documents: - 332995-001EN (I/O datasheet vol. 1) - 332996-002EN (I/O datasheet vol. 2) Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-19 23:49:11 +01:00
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
util/inteltool: Add support for Sunrise Point LP Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-24 06:09:47 +02:00
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
community_count = ARRAY_SIZE(sunrise_lp_communities);
communities = sunrise_lp_communities;
pcr_init(sb);
break;
inteltool: add Lewisburg C62x GPIOs support These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-17 13:54:02 +02:00
case PCI_DEVICE_ID_INTEL_C621:
case PCI_DEVICE_ID_INTEL_C622:
case PCI_DEVICE_ID_INTEL_C624:
case PCI_DEVICE_ID_INTEL_C625:
case PCI_DEVICE_ID_INTEL_C626:
case PCI_DEVICE_ID_INTEL_C627:
case PCI_DEVICE_ID_INTEL_C628:
case PCI_DEVICE_ID_INTEL_C629:
case PCI_DEVICE_ID_INTEL_C624_SUPER:
case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
case PCI_DEVICE_ID_INTEL_C621_SUPER:
case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
case PCI_DEVICE_ID_INTEL_C628_SUPER:
community_count = ARRAY_SIZE(lewisburg_communities);
communities = lewisburg_communities;
pcr_init(sb);
break;
util/inteltool: Add support for Denverton Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-12 19:20:50 +01:00
case PCI_DEVICE_ID_INTEL_DNV_LPC:
community_count = ARRAY_SIZE(denverton_communities);
communities = denverton_communities;
pcr_init(sb);
break;
util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-27 12:27:22 +01:00
case PCI_DEVICE_ID_INTEL_APL_LPC:
community_count = ARRAY_SIZE(apl_communities);
communities = apl_communities;
pcr_init(sb);
break;
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
case PCI_DEVICE_ID_INTEL_H310:
case PCI_DEVICE_ID_INTEL_H370:
case PCI_DEVICE_ID_INTEL_Z390:
case PCI_DEVICE_ID_INTEL_Q370:
case PCI_DEVICE_ID_INTEL_B360:
case PCI_DEVICE_ID_INTEL_C246:
case PCI_DEVICE_ID_INTEL_C242:
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
communities = cannonlake_pch_h_communities;
pad_stepping = 16;
pcr_init(sb);
break;
util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-01-04 15:14:59 +01:00
case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
community_count = ARRAY_SIZE(icelake_pch_h_communities);
communities = icelake_pch_h_communities;
pad_stepping = 16;
pcr_init(sb);
break;
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
default:
return;
}
printf("\n============= GPIOS =============\n\n");
for (; community_count; --community_count)
inteltool: add 300 and C240 Series PCH Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19 11:51:34 +01:00
print_gpio_community(*communities++, pad_stepping);
inteltool: Dump Sunrise Point PCH-H GPIO groups Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-07 12:26:07 +02:00
}