413 lines
12 KiB
C
413 lines
12 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2017 secunet Security Networks AG
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* Copyright (C) 2019 YADRO
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <assert.h>
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#include <inttypes.h>
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#include "inteltool.h"
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#include "pcr.h"
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#include "gpio_names/apollolake.h"
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#include "gpio_names/cannonlake.h"
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#include "gpio_names/icelake.h"
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#include "gpio_names/lewisburg.h"
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#include "gpio_names/sunrise.h"
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#define SBBAR_SIZE (16 * MiB)
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#define PCR_PORT_SIZE (64 * KiB)
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static const char *const denverton_group_north_all_names[] = {
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"NORTH_ALL_GBE0_SDP0",
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"NORTH_ALL_GBE1_SDP0",
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"NORTH_ALL_GBE0_SDP1",
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"NORTH_ALL_GBE1_SDP1",
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"NORTH_ALL_GBE0_SDP2",
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"NORTH_ALL_GBE1_SDP2",
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"NORTH_ALL_GBE0_SDP3",
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"NORTH_ALL_GBE1_SDP3",
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"NORTH_ALL_GBE2_LED0",
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"NORTH_ALL_GBE2_LED1",
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"NORTH_ALL_GBE0_I2C_CLK",
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"NORTH_ALL_GBE0_I2C_DATA",
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"NORTH_ALL_GBE1_I2C_CLK",
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"NORTH_ALL_GBE1_I2C_DATA",
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"NORTH_ALL_NCSI_RXD0",
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"NORTH_ALL_NCSI_CLK_IN",
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"NORTH_ALL_NCSI_RXD1",
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"NORTH_ALL_NCSI_CRS_DV",
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"NORTH_ALL_NCSI_ARB_IN",
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"NORTH_ALL_NCSI_TX_EN",
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"NORTH_ALL_NCSI_TXD0",
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"NORTH_ALL_NCSI_TXD1",
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"NORTH_ALL_NCSI_ARB_OUT",
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"NORTH_ALL_GBE0_LED0",
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"NORTH_ALL_GBE0_LED1",
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"NORTH_ALL_GBE1_LED0",
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"NORTH_ALL_GBE1_LED1",
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"NORTH_ALL_GPIO_0",
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"NORTH_ALL_PCIE_CLKREQ0_N",
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"NORTH_ALL_PCIE_CLKREQ1_N",
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"NORTH_ALL_PCIE_CLKREQ2_N",
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"NORTH_ALL_PCIE_CLKREQ3_N",
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"NORTH_ALL_PCIE_CLKREQ4_N",
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"NORTH_ALL_GPIO_1",
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"NORTH_ALL_GPIO_2",
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"NORTH_ALL_SVID_ALERT_N",
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"NORTH_ALL_SVID_DATA",
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"NORTH_ALL_SVID_CLK",
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"NORTH_ALL_THERMTRIP_N",
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"NORTH_ALL_PROCHOT_N",
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"NORTH_ALL_MEMHOT_N",
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};
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static const struct gpio_group denverton_group_north_all = {
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.display = "------- GPIO Group North All -------",
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.pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_north_all_names,
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};
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static const struct gpio_group *const denverton_community_north_groups[] = {
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&denverton_group_north_all,
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};
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static const struct gpio_community denverton_community_north = {
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.name = "------- GPIO Community 0 -------",
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.pcr_port_id = 0xc2,
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.group_count = ARRAY_SIZE(denverton_community_north_groups),
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.groups = denverton_community_north_groups,
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};
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static const char *const denverton_group_south_dfx_names[] = {
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"SOUTH_DFX_DFX_PORT_CLK0",
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"SOUTH_DFX_DFX_PORT_CLK1",
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"SOUTH_DFX_DFX_PORT0",
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"SOUTH_DFX_DFX_PORT1",
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"SOUTH_DFX_DFX_PORT2",
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"SOUTH_DFX_DFX_PORT3",
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"SOUTH_DFX_DFX_PORT4",
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"SOUTH_DFX_DFX_PORT5",
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"SOUTH_DFX_DFX_PORT6",
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"SOUTH_DFX_DFX_PORT7",
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"SOUTH_DFX_DFX_PORT8",
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"SOUTH_DFX_DFX_PORT9",
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"SOUTH_DFX_DFX_PORT10",
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"SOUTH_DFX_DFX_PORT11",
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"SOUTH_DFX_DFX_PORT12",
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"SOUTH_DFX_DFX_PORT13",
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"SOUTH_DFX_DFX_PORT14",
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"SOUTH_DFX_DFX_PORT15",
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};
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static const struct gpio_group denverton_group_south_dfx = {
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.display = "------- GPIO Group South DFX -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_dfx_names,
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};
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static const char *const denverton_group_south_group0_names[] = {
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"SOUTH_GROUP0_GPIO_12",
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"SOUTH_GROUP0_SMB5_GBE_ALRT_N",
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"SOUTH_GROUP0_PCIE_CLKREQ5_N",
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"SOUTH_GROUP0_PCIE_CLKREQ6_N",
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"SOUTH_GROUP0_PCIE_CLKREQ7_N",
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"SOUTH_GROUP0_UART0_RXD",
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"SOUTH_GROUP0_UART0_TXD",
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"SOUTH_GROUP0_SMB5_GBE_CLK",
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"SOUTH_GROUP0_SMB5_GBE_DATA",
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"SOUTH_GROUP0_ERROR2_N",
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"SOUTH_GROUP0_ERROR1_N",
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"SOUTH_GROUP0_ERROR0_N",
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"SOUTH_GROUP0_IERR_N",
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"SOUTH_GROUP0_MCERR_N",
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"SOUTH_GROUP0_SMB0_LEG_CLK",
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"SOUTH_GROUP0_SMB0_LEG_DATA",
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"SOUTH_GROUP0_SMB0_LEG_ALRT_N",
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"SOUTH_GROUP0_SMB1_HOST_DATA",
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"SOUTH_GROUP0_SMB1_HOST_CLK",
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"SOUTH_GROUP0_SMB2_PECI_DATA",
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"SOUTH_GROUP0_SMB2_PECI_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_DATA",
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"SOUTH_GROUP0_SMB4_CSME0_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
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"SOUTH_GROUP0_USB_OC0_N",
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"SOUTH_GROUP0_FLEX_CLK_SE0",
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"SOUTH_GROUP0_FLEX_CLK_SE1",
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"SOUTH_GROUP0_GPIO_4",
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"SOUTH_GROUP0_GPIO_5",
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"SOUTH_GROUP0_GPIO_6",
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"SOUTH_GROUP0_GPIO_7",
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"SOUTH_GROUP0_SATA0_LED_N",
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"SOUTH_GROUP0_SATA1_LED_N",
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"SOUTH_GROUP0_SATA_PDETECT0",
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"SOUTH_GROUP0_SATA_PDETECT1",
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"SOUTH_GROUP0_SATA0_SDOUT",
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"SOUTH_GROUP0_SATA1_SDOUT",
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"SOUTH_GROUP0_UART1_RXD",
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"SOUTH_GROUP0_UART1_TXD",
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"SOUTH_GROUP0_GPIO_8",
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"SOUTH_GROUP0_GPIO_9",
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"SOUTH_GROUP0_TCK",
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"SOUTH_GROUP0_TRST_N",
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"SOUTH_GROUP0_TMS",
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"SOUTH_GROUP0_TDI",
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"SOUTH_GROUP0_TDO",
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"SOUTH_GROUP0_CX_PRDY_N",
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"SOUTH_GROUP0_CX_PREQ_N",
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"SOUTH_GROUP0_CTBTRIGINOUT",
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"SOUTH_GROUP0_CTBTRIGOUT",
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"SOUTH_GROUP0_DFX_SPARE2",
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"SOUTH_GROUP0_DFX_SPARE3",
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"SOUTH_GROUP0_DFX_SPARE4",
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};
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static const struct gpio_group denverton_group_south_group0 = {
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.display = "------- GPIO Group South Group0 -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_group0_names,
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};
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static const char *const denverton_group_south_group1_names[] = {
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"SOUTH_GROUP1_SUSPWRDNACK",
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"SOUTH_GROUP1_PMU_SUSCLK",
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"SOUTH_GROUP1_ADR_TRIGGER",
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"SOUTH_GROUP1_PMU_SLP_S45_N",
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"SOUTH_GROUP1_PMU_SLP_S3_N",
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"SOUTH_GROUP1_PMU_WAKE_N",
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"SOUTH_GROUP1_PMU_PWRBTN_N",
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"SOUTH_GROUP1_PMU_RESETBUTTON_N",
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"SOUTH_GROUP1_PMU_PLTRST_N",
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"SOUTH_GROUP1_SUS_STAT_N",
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"SOUTH_GROUP1_SLP_S0IX_N",
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"SOUTH_GROUP1_SPI_CS0_N",
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"SOUTH_GROUP1_SPI_CS1_N",
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"SOUTH_GROUP1_SPI_MOSI_IO0",
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"SOUTH_GROUP1_SPI_MISO_IO1",
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"SOUTH_GROUP1_SPI_IO2",
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"SOUTH_GROUP1_SPI_IO3",
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"SOUTH_GROUP1_SPI_CLK",
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"SOUTH_GROUP1_SPI_CLK_LOOPBK",
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"SOUTH_GROUP1_ESPI_IO0",
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"SOUTH_GROUP1_ESPI_IO1",
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"SOUTH_GROUP1_ESPI_IO2",
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"SOUTH_GROUP1_ESPI_IO3",
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"SOUTH_GROUP1_ESPI_CS0_N",
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"SOUTH_GROUP1_ESPI_CLK",
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"SOUTH_GROUP1_ESPI_RST_N",
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"SOUTH_GROUP1_ESPI_ALRT0_N",
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"SOUTH_GROUP1_GPIO_10",
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"SOUTH_GROUP1_GPIO_11",
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"SOUTH_GROUP1_ESPI_CLK_LOOPBK",
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"SOUTH_GROUP1_EMMC_CMD",
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"SOUTH_GROUP1_EMMC_STROBE",
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"SOUTH_GROUP1_EMMC_CLK",
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"SOUTH_GROUP1_EMMC_D0",
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"SOUTH_GROUP1_EMMC_D1",
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"SOUTH_GROUP1_EMMC_D2",
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"SOUTH_GROUP1_EMMC_D3",
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"SOUTH_GROUP1_EMMC_D4",
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"SOUTH_GROUP1_EMMC_D5",
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"SOUTH_GROUP1_EMMC_D6",
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"SOUTH_GROUP1_EMMC_D7",
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"SOUTH_GROUP1_GPIO_3",
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};
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static const struct gpio_group denverton_group_south_group1 = {
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.display = "------- GPIO Group South Group1 -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_group1_names,
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};
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static const struct gpio_group *const denverton_community_south_groups[] = {
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&denverton_group_south_dfx,
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&denverton_group_south_group0,
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&denverton_group_south_group1,
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};
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static const struct gpio_community denverton_community_south = {
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.name = "------- GPIO Community 1 -------",
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.pcr_port_id = 0xc5,
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.group_count = ARRAY_SIZE(denverton_community_south_groups),
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.groups = denverton_community_south_groups,
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};
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static const struct gpio_community *const denverton_communities[] = {
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&denverton_community_north, &denverton_community_south,
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};
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static const char *decode_pad_mode(const struct gpio_group *const group,
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const size_t pad, const uint32_t dw0)
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{
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const size_t pad_mode = dw0 >> 10 & 7;
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const char *const pad_name =
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group->pad_names[pad * group->func_count + pad_mode];
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if (!pad_mode)
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return pad_name[0] == '*' ? "*GPIO" : "GPIO";
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else if (pad_mode < group->func_count)
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return group->pad_names[pad * group->func_count + pad_mode];
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else
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return "RESERVED";
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}
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static void print_gpio_group(const uint8_t pid, size_t pad_cfg,
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const struct gpio_group *const group,
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size_t pad_stepping)
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{
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size_t p;
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printf("%s\n", group->display);
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for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) {
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const uint32_t dw0 = read_pcr32(pid, pad_cfg);
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const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
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const char *const pad_name =
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group->pad_names[p * group->func_count];
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printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg,
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(uint64_t)dw1 << 32 | dw0,
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pad_name[0] == '*' ? &pad_name[1] : pad_name,
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decode_pad_mode(group, p, dw0));
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}
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}
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static void print_gpio_community(const struct gpio_community *const community,
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size_t pad_stepping)
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{
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size_t group, pad_count;
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size_t pad_cfg; /* offset in bytes under this communities PCR port */
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printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
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community->name, (size_t)community->pcr_port_id << 16);
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for (group = 0, pad_count = 0; group < community->group_count; ++group)
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pad_count += community->groups[group]->pad_count;
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assert(pad_count * 8 <= PCR_PORT_SIZE - 0x10);
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pad_cfg = read_pcr32(community->pcr_port_id, 0x0c);
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if (pad_cfg + pad_count * 8 > PCR_PORT_SIZE) {
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fprintf(stderr, "Bad Pad Base Address: 0x%08zx\n", pad_cfg);
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return;
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}
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for (group = 0; group < community->group_count; ++group) {
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print_gpio_group(community->pcr_port_id,
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pad_cfg, community->groups[group],
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pad_stepping);
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pad_cfg += community->groups[group]->pad_count * pad_stepping;
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}
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}
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void print_gpio_groups(struct pci_dev *const sb)
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{
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size_t community_count;
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const struct gpio_community *const *communities;
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size_t pad_stepping = 8;
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_H110:
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case PCI_DEVICE_ID_INTEL_H170:
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case PCI_DEVICE_ID_INTEL_Z170:
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case PCI_DEVICE_ID_INTEL_Q170:
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case PCI_DEVICE_ID_INTEL_Q150:
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case PCI_DEVICE_ID_INTEL_B150:
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case PCI_DEVICE_ID_INTEL_C236:
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case PCI_DEVICE_ID_INTEL_C232:
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case PCI_DEVICE_ID_INTEL_QM170:
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case PCI_DEVICE_ID_INTEL_HM170:
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case PCI_DEVICE_ID_INTEL_CM236:
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community_count = ARRAY_SIZE(sunrise_communities);
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communities = sunrise_communities;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
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community_count = ARRAY_SIZE(sunrise_lp_communities);
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communities = sunrise_lp_communities;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_C621:
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case PCI_DEVICE_ID_INTEL_C622:
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case PCI_DEVICE_ID_INTEL_C624:
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case PCI_DEVICE_ID_INTEL_C625:
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case PCI_DEVICE_ID_INTEL_C626:
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case PCI_DEVICE_ID_INTEL_C627:
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case PCI_DEVICE_ID_INTEL_C628:
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case PCI_DEVICE_ID_INTEL_C629:
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case PCI_DEVICE_ID_INTEL_C624_SUPER:
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case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
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case PCI_DEVICE_ID_INTEL_C621_SUPER:
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case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
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case PCI_DEVICE_ID_INTEL_C628_SUPER:
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community_count = ARRAY_SIZE(lewisburg_communities);
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communities = lewisburg_communities;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_DNV_LPC:
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community_count = ARRAY_SIZE(denverton_communities);
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communities = denverton_communities;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_APL_LPC:
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community_count = ARRAY_SIZE(apl_communities);
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communities = apl_communities;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_H310:
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case PCI_DEVICE_ID_INTEL_H370:
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case PCI_DEVICE_ID_INTEL_Z390:
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case PCI_DEVICE_ID_INTEL_Q370:
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case PCI_DEVICE_ID_INTEL_B360:
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case PCI_DEVICE_ID_INTEL_C246:
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case PCI_DEVICE_ID_INTEL_C242:
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case PCI_DEVICE_ID_INTEL_QM370:
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case PCI_DEVICE_ID_INTEL_HM370:
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case PCI_DEVICE_ID_INTEL_CM246:
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community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
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communities = cannonlake_pch_h_communities;
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pad_stepping = 16;
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pcr_init(sb);
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break;
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case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
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community_count = ARRAY_SIZE(icelake_pch_h_communities);
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communities = icelake_pch_h_communities;
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pad_stepping = 16;
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pcr_init(sb);
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break;
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default:
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return;
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}
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printf("\n============= GPIOS =============\n\n");
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|
|
|
for (; community_count; --community_count)
|
|
print_gpio_community(*communities++, pad_stepping);
|
|
}
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