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coreboot-kgpe-d16/src/soc/intel/skylake/lockdown.c

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soc/intel/skylake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05 15:47:17 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
device/mmio.h: Add include file for MMIO ops MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03 07:01:05 +01:00
#include <device/mmio.h>
soc/intel: Rename <intelblocks/chip.h> The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-27 23:00:30 +02:00
#include <intelblocks/cfg.h>
soc/intel/skylake: Enable common LPC IP Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-29 02:06:01 +02:00
#include <intelblocks/lpc_lib.h>
soc/intel/skylake: lockdown: lock global reset There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17 18:48:00 +02:00
#include <intelblocks/pmclib.h>
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
#include <intelpch/lockdown.h>
soc/intel/skylake: Move PMC lock down config after resource allocation This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 08:38:59 +02:00
#include <soc/pm.h>
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
static void lpc_lockdown_config(int chipset_lockdown)
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
{
treewide: capitalize 'BIOS' Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-16 16:22:52 +01:00
/* Set BIOS Interface Lock, BIOS Lock */
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
soc/intel/skylake: Enable common LPC IP Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-29 02:06:01 +02:00
lpc_set_bios_interface_lock_down();
lpc_set_lock_enable();
}
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
}
soc/intel/skylake: Move PMC lock down config after resource allocation This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 08:38:59 +02:00
static void pmc_lockdown_config(void)
{
uint8_t *pmcbase;
u32 pmsyncreg;
/* PMSYNC */
pmcbase = pmc_mmio_regs();
pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
pmsyncreg |= PMSYNC_LOCK;
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
soc/intel/skylake: lockdown: lock global reset There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17 18:48:00 +02:00
/* Make sure payload/OS can't trigger global reset */
pmc_global_reset_disable_and_lock();
soc/intel/skylake: Move PMC lock down config after resource allocation This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 08:38:59 +02:00
}
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
void soc_lockdown_config(int chipset_lockdown)
soc/intel/skylake: Move DMI lock down config after resource allocation This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-16 15:08:54 +02:00
{
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
/* LPC lock down configuration */
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
lpc_lockdown_config(chipset_lockdown);
soc/intel/skylake: Move DMI lock down config after resource allocation This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-16 15:08:54 +02:00
soc/intel/skylake: Move PMC lock down config after resource allocation This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 08:38:59 +02:00
/* PMC lock down configuration */
pmc_lockdown_config();
soc/intel/skylake: Move LPC lock down config after resource allocation This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14 12:45:33 +02:00
}
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