305 lines
8.6 KiB
C
305 lines
8.6 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <device/device.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <boot/tables.h>
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#include <cbmem.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/dc.h>
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#include "clk_rst.h"
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#include "chip.h"
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#include <soc/display.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x01000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_data_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00210222,
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0x00002200,
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0x00020000,
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};
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static int update_display_mode(struct dc_disp_reg *disp,
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struct soc_nvidia_tegra124_config *config)
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{
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u32 val;
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u32 rate;
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u32 div;
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writel(0x0, &disp->disp_timing_opt);
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writel(config->vref_to_sync << 16 | config->href_to_sync,
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&disp->ref_to_sync);
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writel(config->vsync_width << 16 | config->hsync_width, &disp->sync_width);
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writel(config->vback_porch << 16 | config->hback_porch, &disp->back_porch);
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writel(config->vfront_porch << 16 | config->hfront_porch,
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&disp->front_porch);
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writel(config->xres | (config->yres << 16), &disp->disp_active);
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val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
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val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
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writel(val, &disp->data_enable_opt);
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val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
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val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
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val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
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writel(val, &disp->disp_interface_ctrl);
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/*
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* The pixel clock divider is in 7.1 format (where the bottom bit
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* represents 0.5). Here we calculate the divider needed to get from
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* the display clock (typically 600MHz) to the pixel clock. We round
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* up or down as requried.
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* We use pllp for now.
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*/
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rate = 600 * 1000000;
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div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
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printk(BIOS_SPEW, "Display clock %d, divider %d\n", rate, div);
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writel(0x00010001, &disp->shift_clk_opt);
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val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
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val |= div << SHIFT_CLK_DIVIDER_SHIFT;
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writel(val, &disp->disp_clk_ctrl);
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return 0;
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}
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static int setup_window(struct disp_ctl_win *win,
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struct soc_nvidia_tegra124_config *config)
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{
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int log2_bpp = log2(config->framebuffer_bits_per_pixel);
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win->x = 0;
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win->y = 0;
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win->w = config->xres;
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win->h = config->yres;
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win->out_x = 0;
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win->out_y = 0;
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win->out_w = config->xres;
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win->out_h = config->yres;
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win->phys_addr = config->framebuffer_base;
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win->stride = config->xres * (1 << log2_bpp) / 8;
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printk(BIOS_SPEW, "%s: depth = %d\n", __func__, log2_bpp);
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switch (log2_bpp) {
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case 5:
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case 24:
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win->fmt = COLOR_DEPTH_R8G8B8A8;
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win->bpp = 32;
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break;
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case 4:
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win->fmt = COLOR_DEPTH_B5G6R5;
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win->bpp = 16;
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break;
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default:
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printk(BIOS_SPEW, "Unsupported LCD bit depth");
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return -1;
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}
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return 0;
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}
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static void update_window(struct display_controller *dc,
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struct disp_ctl_win *win,
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struct soc_nvidia_tegra124_config *config)
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{
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u32 h_dda, v_dda;
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u32 val;
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val = readl(&dc->cmd.disp_win_header);
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val |= WINDOW_A_SELECT;
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writel(val, &dc->cmd.disp_win_header);
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writel(win->fmt, &dc->win.color_depth);
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clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
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BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
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val = win->out_x << H_POSITION_SHIFT;
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val |= win->out_y << V_POSITION_SHIFT;
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writel(val, &dc->win.pos);
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val = win->out_w << H_SIZE_SHIFT;
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val |= win->out_h << V_SIZE_SHIFT;
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writel(val, &dc->win.size);
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val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
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val |= win->h << V_PRESCALED_SIZE_SHIFT;
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writel(val, &dc->win.prescaled_size);
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writel(0, &dc->win.h_initial_dda);
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writel(0, &dc->win.v_initial_dda);
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h_dda = (win->w * 0x1000) / MAX(win->out_w - 1, 1);
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v_dda = (win->h * 0x1000) / MAX(win->out_h - 1, 1);
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val = h_dda << H_DDA_INC_SHIFT;
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val |= v_dda << V_DDA_INC_SHIFT;
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writel(val, &dc->win.dda_increment);
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writel(win->stride, &dc->win.line_stride);
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writel(0, &dc->win.buf_stride);
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val = WIN_ENABLE;
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if (win->bpp < 24)
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val |= COLOR_EXPAND;
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writel(val, &dc->win.win_opt);
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writel((u32) win->phys_addr, &dc->winbuf.start_addr);
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writel(win->x, &dc->winbuf.addr_h_offset);
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writel(win->y, &dc->winbuf.addr_v_offset);
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writel(0xff00, &dc->win.blend_nokey);
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writel(0xff00, &dc->win.blend_1win);
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
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val |= GENERAL_UPDATE | WIN_A_UPDATE;
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writel(val, &dc->cmd.state_ctrl);
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}
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/* this is really aimed at the lcd panel. That said, there are two display
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* devices on this part and we may someday want to extend it for other boards.
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*/
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void display_startup(device_t dev)
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{
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u32 val;
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int i;
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struct soc_nvidia_tegra124_config *config = dev->chip_info;
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struct display_controller *dc = (void *)config->display_controller;
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struct disp_ctl_win window;
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/* should probably just make it all MiB ... in future */
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u32 framebuffer_size_mb = config->framebuffer_size / MiB;
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u32 framebuffer_base_mb= config->framebuffer_base / MiB;
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printk(BIOS_SPEW,
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"%s: xres %d yres %d framebuffer_bits_per_pixel %d\n",
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__func__,
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config->xres, config->yres, config->framebuffer_bits_per_pixel);
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if (framebuffer_size_mb == 0){
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framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
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(config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
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}
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if (! framebuffer_base_mb)
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framebuffer_base_mb = FB_BASE_MB;
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mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
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config->cache_policy);
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/* Enable flushing after LCD writes if requested */
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/* I don't understand this part yet.
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lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
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*/
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printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
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framebuffer_base_mb + framebuffer_size_mb);
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/* GPIO magic here if needed to start powering up things. You
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* really only want to enable vdd, wait a bit, and then enable
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* the panel. However ... the timings in the tegra20 dts make
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* no sense to me. I'm pretty sure they're wrong.
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* The panel_vdd is done in the romstage, so we need only
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* light things up here once we're sure it's all working.
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*/
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setbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1 | CLK_L_HOST1X);
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clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4,
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CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000));
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/* u-boot uses PLLC for DISP1.
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* But the u-boot code does not work and we don't set up PLLC anyway.
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* PLLP seems quite good enough, so run with that for now. */
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clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */,
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CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000));
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udelay(2);
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clrbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1|CLK_L_HOST1X);
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writel(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl);
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writel(0x0000011a, &dc->cmd.cont_syncpt_vsync);
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writel(0x00000000, &dc->cmd.int_type);
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writel(0x00000000, &dc->cmd.int_polarity);
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writel(0x00000000, &dc->cmd.int_mask);
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writel(0x00000000, &dc->cmd.int_enb);
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val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
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val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
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val |= PM1_ENABLE;
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writel(val, &dc->cmd.disp_pow_ctrl);
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val = readl(&dc->cmd.disp_cmd);
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val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
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writel(val, &dc->cmd.disp_cmd);
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writel(0x00000020, &dc->disp.mem_high_pri);
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writel(0x00000001, &dc->disp.mem_high_pri_timer);
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for (i = 0; i < PIN_REG_COUNT; i++) {
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writel(rgb_enb_tab[i], &dc->com.pin_output_enb[i]);
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writel(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]);
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writel(rgb_data_tab[i], &dc->com.pin_output_data[i]);
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}
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for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
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writel(rgb_sel_tab[i], &dc->com.pin_output_sel[i]);
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if (config->pixel_clock)
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update_display_mode(&dc->disp, config);
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if (!setup_window(&window, config))
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update_window(dc, &window, config);
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}
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