coreboot-kgpe-d16/src/soc/mediatek/mt8195/bootblock.c

/* SPDX-License-Identifier: GPL-2.0-only */

#include <bootblock_common.h>
#include <soc/mmu_operations.h>
#include <soc/pll.h>
#include <soc/wdt.h>

void bootblock_soc_init(void)
{
	mtk_mmu_init();
	mtk_wdt_init();
	mt_pll_init();
}
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> 2021-01-07 13:25:54 +01:00			`/* SPDX-License-Identifier: GPL-2.0-only */`

			`#include <bootblock_common.h>`
			`#include <soc/mmu_operations.h>`
soc/mediatek/mt8195: Add PLL and clock init support Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> 2021-02-03 09:20:57 +01:00			`#include <soc/pll.h>`
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> 2021-04-22 07:34:04 +02:00			`#include <soc/wdt.h>`
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> 2021-01-07 13:25:54 +01:00
			`void bootblock_soc_init(void)`
			`{`
			`mtk_mmu_init();`
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> 2021-04-22 07:34:04 +02:00			`mtk_wdt_init();`
soc/mediatek/mt8195: Add PLL and clock init support Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> 2021-02-03 09:20:57 +01:00			`mt_pll_init();`
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> 2021-01-07 13:25:54 +01:00			`}`