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coreboot-kgpe-d16/src/soc/intel/quark/northcluster.c

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soc/intel/quark: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3fdfa159194cccf15c0284700f554d2241dad6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05 15:47:14 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
soc/intel/quark: Establish the Memory Map Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 00:10:35 +01:00
#include <cbmem.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/iomap.h>
#include <soc/ramstage.h>
#define RES_IN_KIB(r) ((r) >> 10)
soc/intel/quark: Get rid of device_t Use of device_t has been abandoned in ramstage. Change-Id: I102c9b9b1066064589149388d5ebbcd6d0d81fa7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-25 13:11:37 +02:00
static void nc_read_resources(struct device *dev)
soc/intel/quark: Establish the Memory Map Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 00:10:35 +01:00
{
unsigned long base_k;
int index = 0;
unsigned long size_k;
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
/* 0 -> 0xa0000 */
base_k = 0;
size_k = 0xa0000 - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
/*
* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xdffff: RAM
* 0xe0000 - 0xfffff: ROM shadow
*/
base_k += size_k;
size_k = 0xc0000 - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
base_k += size_k;
size_k = 0x100000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0x100000 -> cbmem_top - cacheable and usable */
base_k += size_k;
size_k = (unsigned long)cbmem_top() - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
soc/intel/quark: Reserve non-MMIO space Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13856 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28 20:30:17 +01:00
/* cbmem_top -> 0xc0000000 - reserved */
base_k += size_k;
size_k = 0xc0000000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0xc0000000 -> 4GiB is mmio. */
soc/intel/quark: Establish the Memory Map Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 00:10:35 +01:00
base_k += size_k;
size_k = 0x100000000ull - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
}
static struct device_operations nc_ops = {
soc/{amd,intel}: Remove needless '&' on function pointers Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-11-27 12:23:48 +01:00
.read_resources = nc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
soc/intel/quark: Establish the Memory Map Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 00:10:35 +01:00
};
static const struct pci_driver systemagent_driver __pci_driver = {
.ops = &nc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = QUARK_MC_DEVICE_ID
};
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