2017-05-23 05:35:16 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2017-06-19 01:35:27 +02:00
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#include "ec.h"
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2017-05-23 05:35:16 +02:00
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/* DefinitionBlock Statement */
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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"GOOGLE ", /* OEMID */
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"COREBOOT", /* TABLE ID */
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* as needed */
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2017-06-19 01:35:27 +02:00
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/* global NVS and variables */
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#include <globalnvs.asl>
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2017-05-23 05:35:16 +02:00
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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/* Describe the USB Overcurrent pins */
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2017-11-07 21:45:29 +01:00
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#include "variant/acpi/usb_oc.asl"
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2017-05-23 05:35:16 +02:00
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/* PCI IRQ mapping for the Southbridge */
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#include <pcie.asl>
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/* Describe the processor tree (\_PR) */
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#include <cpu.asl>
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/* Contains the supported sleep states for this chipset */
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#include <sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* IRQ Routing mapping for this platform (in \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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}
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <fch.asl>
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <pci_int.asl>
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/* Describe the devices in the Southbridge */
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#include "acpi/carrizo_fch.asl"
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} /* End \_SB scope */
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2017-06-19 01:35:27 +02:00
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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2017-05-23 05:35:16 +02:00
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/* Describe SMBUS for the Southbridge */
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#include <smbus.asl>
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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}
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/* End of ASL file */
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