54 lines
1.3 KiB
Text
54 lines
1.3 KiB
Text
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define INCLUDE_LPE 1
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#define INCLUDE_SCC 1
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#define INCLUDE_EHCI 1
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#define INCLUDE_XHCI 1
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#define INCLUDE_LPSS 1
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/fsp_baytrail/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
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#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
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#include "acpi/mainboard.asl"
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}
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