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mainboard/intel/minnowmax: Add MinnowMax mainboard 

MinnowMax board using Intel's Bay Trail FSP

Working:
- Booting from SATA / USB / (USB3 with latest SeaBIOS)

Not working:
- Boot from SD
- S3 Suspend / Resume

***** To configure the FSP *****
Download the Bay Trail FSP and the binary config tool:

Modify the standard Bay Trail FSP:
run the bct tool with the command line options:
bct --bin <Bay Trail FSP Binary> \
	--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
	--bout <path to save the updated FSP to>

Here are the required changes for modifying the FSP manually:
	Enable Memory Down: Enabled
	DRAM Speed: 1066 MHz
	DIMM_DWidth: x16
	DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
	tCL: 7
	tRP_tRCD: 7
	tWR: 8
	tRRD: 6
	tRTP: 4
	tFAW: 27
Other FSP values can remain the same.

***** To configure the vbios *****
The vbios is in the Bay Trail FSP package.
Download Intel's "Binary Modification Program" (BMP)
Use it to disable all ports except HDMI on port B.

Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6429
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2014-07-28 14:22:32 -06:00 committed by Martin Roth
parent 83da50173c
commit e6df041b8b
17 changed files with 1232 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/intel/Kconfig
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@ -17,6 +17,8 @@ config BOARD_INTEL_EMERALDLAKE2
bool "Emerald Lake 2 CRB"
config BOARD_INTEL_JARRELL
bool "Jarrell (SE7520JR2)"
config BOARD_INTEL_MINNOWMAX
bool "Minnow Max"
config BOARD_INTEL_MOHONPEAK
bool "Mohon Peak CRB"
config BOARD_INTEL_MTARVON
@ -40,6 +42,7 @@ source "src/mainboard/intel/eagleheights/Kconfig"
source "src/mainboard/intel/emeraldlake2/Kconfig"
source "src/mainboard/intel/baskingridge/Kconfig"
source "src/mainboard/intel/jarrell/Kconfig"
source "src/mainboard/intel/minnowmax/Kconfig"
source "src/mainboard/intel/mohonpeak/Kconfig"
source "src/mainboard/intel/mtarvon/Kconfig"
source "src/mainboard/intel/truxton/Kconfig"

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src/mainboard/intel/minnowmax/Kconfig Normal file
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@ -0,0 +1,127 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if BOARD_INTEL_MINNOWMAX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_INTEL_FSP_BAYTRAIL
select BOARD_ROMSIZE_KB_4096
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select OVERRIDE_MRC_CACHE_LOC
select TSC_MONOTONIC_TIMER
config MAINBOARD_DIR
string
default "intel/minnowmax"
config INCLUDE_ME
bool
default n
config LOCK_MANAGEMENT_ENGINE
bool
default n
config MAINBOARD_PART_NUMBER
string
default "Minnow Max 2GB" if MINNOWMAX_2GB_SKU
default "Minnow Max 1GB"
choice
prompt "Memory SKU to build"
default MINNOWMAX_1GB_SKU
config MINNOWMAX_1GB_SKU
bool "1GB"
config MINNOWMAX_2GB_SKU
bool "2GB"
endchoice
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 16
config CACHE_ROM_SIZE_OVERRIDE
hex
default 0x800000
config FSP_LOC
hex
default 0xfffc0000
config FSP_FILE
string
default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_2gb.bin" if MINNOWMAX_2GB_SKU
default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_1gb.bin"
config MRC_CACHE_LOC_OVERRIDE
hex
default 0xfff90000
depends on ENABLE_FSP_FAST_BOOT
config CBFS_SIZE
hex
default 0x00300000
config DRIVERS_PS2_KEYBOARD
bool
default n
config CONSOLE_POST
bool
default y
config ENABLE_FSP_FAST_BOOT
bool
depends on HAVE_FSP_BIN
default y
config VIRTUAL_ROM_SIZE
hex
depends on ENABLE_FSP_FAST_BOOT
default 0x800000
config POST_IO
bool
default n
config POST_DEVICE
bool
default n
config VGA_BIOS
bool
default n
config VGA_BIOS_FILE
string
default "../intel/mainboard/intel/minnowmax/Vga.dat" if VGA_BIOS
endif # BOARD_INTEL_MINNOWMAX

21
src/mainboard/intel/minnowmax/Makefile.inc Normal file
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@ -0,0 +1,21 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-y += gpio.c
ramstage-y += irqroute.c

0
src/mainboard/intel/minnowmax/acpi/ec.asl Normal file
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25
src/mainboard/intel/minnowmax/acpi/mainboard.asl Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}

0
src/mainboard/intel/minnowmax/acpi/superio.asl Normal file
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0
src/mainboard/intel/minnowmax/acpi/video.asl Normal file
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282
src/mainboard/intel/minnowmax/acpi_tables.c Normal file
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@ -0,0 +1,282 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <lib.h> // hexdump
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <baytrail/acpi.h>
#include <baytrail/nvs.h>
#include <baytrail/iomap.h>
extern const unsigned char AmlCode[];
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
acpi_init_gnvs(gnvs);
/* No TPM Present */
gnvs->tpmp = 0;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
current = acpi_madt_irq_overrides(current);
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current,
const char *oem_table_id)
{
generate_cpu_entries();
return (unsigned long) (acpigen_get_current());
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
#define ALIGN_CURRENT current = (ALIGN(current, 16))
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
int i;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *ssdt;
acpi_header_t *ssdt2;
acpi_header_t *dsdt;
global_nvs_t *gnvs;
current = start;
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
ALIGN_CURRENT;
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
ALIGN_CURRENT;
xsdt = (acpi_xsdt_t *) current;
current += sizeof(acpi_xsdt_t);
ALIGN_CURRENT;
/* clear all table memory */
memset((void *) start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
acpi_write_xsdt(xsdt);
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
acpi_create_facs(facs);
printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs,
facs->length);
dsdt = (acpi_header_t *) current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
ALIGN_CURRENT;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt,
dsdt->length);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
ALIGN_CURRENT;
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt,
fadt->header.length);
/*
* We explicitly add these tables later on:
*/
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
ALIGN_CURRENT;
acpi_create_intel_hpet(hpet);
acpi_add_table(rsdp, hpet);
printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet,
hpet->header.length);
/* If we want to use HPET Timers Linux wants an MADT */
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, madt);
printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt,
madt->header.length);
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg,
mcfg->header.length);
/* Update GNVS pointer into CBMEM */
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n");
gnvs = (global_nvs_t *)current;
}
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> %p\n", i, gnvs);
*(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs;
acpi_save_gnvs((unsigned long)gnvs);
break;
}
}
/* And fill it */
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
#if CONFIG_HAVE_SMI_HANDLER
smm_setup_structures(gnvs, NULL, NULL);
#endif
current += sizeof(global_nvs_t);
ALIGN_CURRENT;
/* We patched up the DSDT, so we need to recalculate the checksum */
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt,
dsdt->length);
ssdt = (acpi_header_t *)current;
memset(ssdt, 0, sizeof(acpi_header_t));
acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
if (ssdt->length) {
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt,
ssdt->length);
ALIGN_CURRENT;
} else {
ssdt = NULL;
printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n");
}
ssdt2 = (acpi_header_t *)current;
memset(ssdt2, 0, sizeof(acpi_header_t));
acpi_create_serialio_ssdt(ssdt2);
if (ssdt2->length) {
current += ssdt2->length;
acpi_add_table(rsdp, ssdt2);
printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2,
ssdt2->length);
ALIGN_CURRENT;
} else {
ssdt2 = NULL;
printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n");
}
printk(BIOS_DEBUG, "current = %lx\n", current);
#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES)
printk(BIOS_DEBUG, "rsdp\n");
hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "hpet\n");
hexdump(BIOS_DEBUG, hpet, hpet->header.length);
printk(BIOS_DEBUG, "madt\n");
hexdump(BIOS_DEBUG, madt, madt->header.length);
printk(BIOS_DEBUG, "mcfg\n");
hexdump(BIOS_DEBUG, mcfg, mcfg->header.length);
printk(BIOS_DEBUG, "dsdt\n");
hexdump(BIOS_DEBUG, dsdt, dsdt->length);
if (ssdt != NULL) {
printk(BIOS_DEBUG, "ssdt\n");
hexdump(BIOS_DEBUG, ssdt, ssdt->length);
}
if (ssdt2 != NULL) {
printk(BIOS_DEBUG, "ssdt2\n");
hexdump(BIOS_DEBUG, ssdt2, ssdt2->length);
}
printk(BIOS_DEBUG, "fadt\n");
hexdump(BIOS_DEBUG, fadt, fadt->header.length);
printk(BIOS_DEBUG, "facs\n");
hexdump(BIOS_DEBUG, facs, facs->length);
#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

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src/mainboard/intel/minnowmax/cmos.layout Normal file
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@ -0,0 +1,139 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
388 4 r 0 reboot_bits
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused
# MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
#save timestamps in pre-ram boot areas
1719 64 h 0 timestamp_value1
1783 64 h 0 timestamp_value2
1847 64 h 0 timestamp_value3
1911 64 h 0 timestamp_value4
1975 64 h 0 timestamp_value5
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums
checksum 392 415 984

80
src/mainboard/intel/minnowmax/devicetree.cb Normal file
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@ -0,0 +1,80 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip soc/intel/fsp_baytrail
#### ACPI Register Settings ####
register "fadt_pm_profile" = "PM_UNSPECIFIED"
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
#### FSP register settings ####
register "SataMode" = "SATA_MODE_AHCI"
register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT"
register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
register "ApertureSize" = "APERTURE_SIZE_DEFAULT"
register "GttSize" = "GTT_SIZE_DEFAULT"
register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # 8086 0F00 - SoC router -
device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
device pci 03.0 off end # 8086 0F38 - MIPI -
device pci 10.0 off end # 8086 0F14 - EMMC Port -
device pci 11.0 off end # 8086 0F15 - SDIO Port -
device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC
device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
device pci 17.0 off end # 8086 0F50 - MMC Port -
device pci 18.0 on end # 8086 0F40 - SIO - DMA -
device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
device pci 1a.0 on end # 8086 0F18 - TXE -
device pci 1b.0 off end # 8086 0F04 - HD Audio -
device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) -
device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
device pci 1d.0 off end # 8086 0F34 - USB EHCI -
device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
device pci 1e.5 on end # 8086 0F0E - SPI LSEC
device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
end
end

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src/mainboard/intel/minnowmax/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define INCLUDE_LPE 1
#define INCLUDE_SCC 1
#define INCLUDE_EHCI 1
#define INCLUDE_XHCI 1
#define INCLUDE_LPSS 1
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Some generic macros
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
}
}
/* Chipset specific sleep states */
#include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
#include "acpi/mainboard.asl"
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/acpi.h>
#include <baytrail/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
acpi_fill_in_fadt(fadt,facs,dsdt);
/* Platform specific customizations go here */
header->checksum = 0;
header->checksum =
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <baytrail/gpio.h>
#include "irqroute.h"
/*
* For multiplexed functions, look in EDS:
* 10.3 Ball Name and Function by Location
*
* The pads list is in the BWG_VOL2 Rev1p2:
* Note that Pad # is not the same as GPIO#
* 37 GPIO Handling:
* Table 37-1. SCORE Pads List
* Table 37-2. SSUSORE Pads List
*/
/* NCORE GPIOs */
static const struct soc_gpio_map gpncore_gpio_map[] = {
GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */
GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */
GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */
GPIO_NC, /* GPIO_S0_NC[03] - No Connect */
GPIO_NC, /* GPIO_S0_NC[04] - No Connect */
GPIO_NC, /* GPIO_S0_NC[05] - No Connect */
GPIO_NC, /* GPIO_S0_NC[06] - No Connect */
GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */
GPIO_NC, /* GPIO_S0_NC[08] - No Connect */
GPIO_NC, /* GPIO_S0_NC[09] - No Connect */
GPIO_NC, /* GPIO_S0_NC[10] - No Connect */
GPIO_NC, /* GPIO_S0_NC[11] - No Connect */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */
GPIO_NC, /* GPIO_S0_NC[13] - No Connect */
GPIO_NC, /* GPIO_S0_NC[14] - No Connect */
GPIO_NC, /* GPIO_S0_NC[15] - No Connect */
GPIO_NC, /* GPIO_S0_NC[16] - No Connect */
GPIO_NC, /* GPIO_S0_NC[17] - No Connect */
GPIO_NC, /* GPIO_S0_NC[18] - No Connect */
GPIO_NC, /* GPIO_S0_NC[19] - No Connect */
GPIO_NC, /* GPIO_S0_NC[20] - No Connect */
GPIO_NC, /* GPIO_S0_NC[21] - No Connect */
GPIO_NC, /* GPIO_S0_NC[22] - No Connect */
GPIO_NC, /* GPIO_S0_NC[23] - No Connect */
GPIO_NC, /* GPIO_S0_NC[24] - No Connect */
GPIO_NC, /* GPIO_S0_NC[25] - No Connect */
GPIO_NC, /* GPIO_S0_NC[26] - No Connect */
GPIO_END
};
/* SCORE GPIOs (GPIO_S0_SC_XX)*/
static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */
GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */
GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */
GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */
GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */
GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */
GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */
GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */
GPIO_NC, /* GPIO_S0_SC[008] - No Connect */
GPIO_NC, /* GPIO_S0_SC[009] - No Connect */
GPIO_NC, /* GPIO_S0_SC[010] - No Connect */
GPIO_NC, /* GPIO_S0_SC[011] - No Connect */
GPIO_NC, /* GPIO_S0_SC[012] - No Connect */
GPIO_NC, /* GPIO_S0_SC[013] - No Connect */
GPIO_NC, /* GPIO_S0_SC[014] - No Connect */
GPIO_NC, /* GPIO_S0_SC[015] - No Connect */
GPIO_NC, /* GPIO_S0_SC[016] - No Connect */
GPIO_NC, /* GPIO_S0_SC[017] - No Connect */
GPIO_NC, /* GPIO_S0_SC[018] - No Connect */
GPIO_NC, /* GPIO_S0_SC[019] - No Connect */
GPIO_NC, /* GPIO_S0_SC[020] - No Connect */
GPIO_NC, /* GPIO_S0_SC[021] - No Connect */
GPIO_NC, /* GPIO_S0_SC[022] - No Connect */
GPIO_NC, /* GPIO_S0_SC[023] - No Connect */
GPIO_NC, /* GPIO_S0_SC[024] - No Connect */
GPIO_NC, /* GPIO_S0_SC[025] - No Connect */
GPIO_NC, /* GPIO_S0_SC[026] - No Connect */
GPIO_NC, /* GPIO_S0_SC[027] - No Connect */
GPIO_NC, /* GPIO_S0_SC[028] - No Connect */
GPIO_NC, /* GPIO_S0_SC[029] - No Connect */
GPIO_NC, /* GPIO_S0_SC[030] - No Connect */
GPIO_NC, /* GPIO_S0_SC[031] - No Connect */
GPIO_NC, /* GPIO_S0_SC[032] - No Connect */
GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */
GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */
GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */
GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */
GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */
GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */
GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */
GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */
GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */
GPIO_NC, /* GPIO_S0_SC[042] - No Connect */
GPIO_NC, /* GPIO_S0_SC[043] - No Connect */
GPIO_NC, /* GPIO_S0_SC[044] - No Connect */
GPIO_NC, /* GPIO_S0_SC[045] - No Connect */
GPIO_NC, /* GPIO_S0_SC[046] - No Connect */
GPIO_NC, /* GPIO_S0_SC[047] - No Connect */
GPIO_NC, /* GPIO_S0_SC[048] - No Connect */
GPIO_NC, /* GPIO_S0_SC[049] - No Connect */
GPIO_NC, /* GPIO_S0_SC[050] - No Connect */
GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */
GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */
GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */
GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) */
GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */
GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) */
GPIO_FUNC0, /* GPIO_S0_SC[059] - HDMI_DCDC_ENB */
GPIO_FUNC0, /* GPIO_S0_SC[060] - HDMI_LDSW_ENB */
GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */
GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */
GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */
GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */
GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */
GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */
GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */
GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */
GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */
GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */
GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */
GPIO_FUNC1, /* GPIO_S0_SC[072] - SIO_UART1_RTSB */
GPIO_FUNC1, /* GPIO_S0_SC[073] - SIO_UART1_CTSB */
GPIO_FUNC1, /* GPIO_S0_SC[074] - SIO_UART2_RXD */
GPIO_FUNC1, /* GPIO_S0_SC[075] - SIO_UART2_TXD */
GPIO_NC, /* GPIO_S0_SC[076] - No Connect */
GPIO_NC, /* GPIO_S0_SC[077] - No Connect */
GPIO_NC, /* GPIO_S0_SC[078] - No Connect */
GPIO_NC, /* GPIO_S0_SC[079] - No Connect */
GPIO_FUNC1, /* GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) */
GPIO_FUNC1, /* GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) */
GPIO_NC, /* GPIO_S0_SC[082] - No Connect */
GPIO_NC, /* GPIO_S0_SC[083] - No Connect */
GPIO_NC, /* GPIO_S0_SC[084] - No Connect */
GPIO_NC, /* GPIO_S0_SC[085] - No Connect */
GPIO_NC, /* GPIO_S0_SC[086] - No Connect */
GPIO_NC, /* GPIO_S0_SC[087] - No Connect */
GPIO_FUNC1, /* GPIO_S0_SC[088] - LSS_I2C_SDA */
GPIO_FUNC1, /* GPIO_S0_SC[089] - LSS_I2C_SCL */
GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */
GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */
GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[092] - TP13 */
GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[093] - TP16 */
GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */
GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */
GPIO_NC, /* GPIO_S0_SC[096] - No Connect */
GPIO_NC, /* GPIO_S0_SC[097] - No Connect */
GPIO_NC, /* GPIO_S0_SC[098] - No Connect */
GPIO_NC, /* GPIO_S0_SC[099] - No Connect */
GPIO_NC, /* GPIO_S0_SC[100] - No Connect */
GPIO_NC, /* GPIO_S0_SC[101] - No Connect */
GPIO_END
};
/* SSUS GPIOs (GPIO_S5) */
static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[00] - SOC_GPIO_S5_0 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[01] - SOC_GPIO_S5_1 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */
GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */
GPIO_NC, /* GPIO_S5[04] - No Connect */
GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 */
GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */
GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */
GPIO_OUT_HIGH, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */
GPIO_OUT_HIGH, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */
GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */
GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */
GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */
GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */
GPIO_FUNC0, /* GPIO_S5[15] - PMC_PCIE_WAKE_R */
GPIO_FUNC0, /* GPIO_S5[16] - PMC_PWRBTN */
GPIO_NC1, /* GPIO_S5[17] - No Connect */
GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */
GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */
GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */
GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */
GPIO_NC, /* GPIO_S5[22] - No Connect */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[23] - XDP_H_OBSDATA_A0 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[24] - XDP_H_OBSDATA_A1 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[25] - XDP_H_OBSDATA_A2 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[26] - XDP_H_OBSDATA_A3 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[27] - EXP_GPIO1 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[28] - EXP_GPIO2 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[29] - EXP_GPIO3 */
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[30] - EXP_GPIO4 */
GPIO_NC, /* GPIO_S5[31] - No Connect */
GPIO_NC, /* GPIO_S5[32] - No Connect */
GPIO_NC, /* GPIO_S5[33] - No Connect */
GPIO_NC, /* GPIO_S5[34] - No Connect */
GPIO_NC, /* GPIO_S5[35] - No Connect */
GPIO_NC, /* GPIO_S5[36] - No Connect */
GPIO_NC, /* GPIO_S5[37] - No Connect */
GPIO_NC, /* GPIO_S5[38] - No Connect */
GPIO_NC, /* GPIO_S5[39] - No Connect */
GPIO_NC, /* GPIO_S5[40] - No Connect */
GPIO_NC, /* GPIO_S5[41] - No Connect */
GPIO_NC, /* GPIO_S5[42] - No Connect */
GPIO_NC, /* GPIO_S5[43] - No Connect */
GPIO_END
};
static struct soc_gpio_config gpio_config = {
.ncore = gpncore_gpio_map,
.score = gpscore_gpio_map,
.ssus = gpssus_gpio_map,
.core_dirq = NULL,
.sus_dirq = NULL,
};
struct soc_gpio_config* mainboard_get_gpios(void)
{
return &gpio_config;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "irqroute.h"
DEFINE_IRQ_ROUTES;

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef IRQROUTE_H
#define IRQROUTE_H
#include <soc/intel/fsp_baytrail/baytrail/irq.h>
#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
/*
*IR02h GFX INT(A) - PIRQ A
*IR10h EMMC INT(ABCD) - PIRQ DEFG
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
*IR17h MMC INT(A) - PIRQ F
*IR18h SIO INT(ABCD) - PIRQ BADC
*IR1Ah TXE INT(A) - PIRQ F
*IR1Bh HD Audio INT(A) - PIRQ G
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
*IR1Dh EHCI INT(A) - PIRQ D
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
*/
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
/*
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
* Reserved: 0, 1, 2, 8, 13
* PS2 keyboard: 12
* ACPI/SCI: 9
* Floppy: 6
*/
#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, 4), \
PIRQ_PIC(B, 5), \
PIRQ_PIC(C, 7), \
PIRQ_PIC(D, 10), \
PIRQ_PIC(E, 11), \
PIRQ_PIC(F, 12), \
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)
#endif /* IRQROUTE_H */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
/*
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
*/
static void mainboard_enable(device_t dev)
{
}
/*
* mainboard_final is executed as one of the last items before loading the
* payload.
*
* This is the latest point to add customization.
*/
static void mainboard_final(void *chip_info)
{
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
.final = mainboard_final,
};

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stddef.h>
#include <arch/cpu.h>
#include <lib.h>
#include <arch/io.h>
#include <arch/cbfs.h>
#include <arch/stages.h>
#include <console/console.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <baytrail/gpio.h>
#include <baytrail/iomap.h>
#include <baytrail/lpc.h>
#include <baytrail/pci_devs.h>
#include <baytrail/romstage.h>
#include <baytrail/acpi.h>
#include <baytrail/baytrail.h>
#include <drivers/intel/fsp/fsp_util.h>
/**
* /brief mainboard call for setup that needs to be done before fsp init
*
*/
void early_mainboard_romstage_entry()
{
}
/**
* Get function disables - most of these will be done automatically
* @param fd_mask
* @param fd2_mask
*/
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
{
}
/**
* /brief mainboard call for setup that needs to be done after fsp init
*
*/
void late_mainboard_romstage_entry()
{
}
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
/* Disable 2nd DIMM */
UpdData->PcdMrcInitSPDAddr2 = 0x00;
return;
}