2014-10-15 21:51:47 +02:00
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package main
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type sandybridgemc struct {
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variant string
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}
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func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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inteltool := ctx.InfoSource.GetInteltool()
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/* FIXME:XX Move this somewhere else. */
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MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
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MainboardEnable += (` /* FIXME: fix those values*/
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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`)
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pchLVDS := inteltool.IGD[0xe1180]
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dualChannel := pchLVDS&(3<<2) == (3 << 2)
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pipe := (pchLVDS >> 30) & 1
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link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
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link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
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link_factor := float32(link_m1) / float32(link_n1)
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fp0 := inteltool.IGD[0xc6040+8*pipe]
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dpll := inteltool.IGD[0xc6014+4*pipe]
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pixel_m2 := fp0 & 0xff
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pixel_m1 := (fp0>>8)&0xff + 2
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pixel_p1 := uint32(1)
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for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 {
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pixel_p1++
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}
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pixel_n := ((fp0 >> 16) & 0xff) + 2
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pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0)
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if !dualChannel {
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pixel_frequency /= 2
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}
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link_frequency := pixel_frequency / link_factor
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DevTree = DevTreeNode{
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Chip: "northbridge/intel/sandybridge",
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MissingParent: "northbridge",
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Comment: "FIXME: check gfx.ndid and gfx.did",
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Registers: map[string]string{
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"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
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"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
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"gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
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"gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
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"gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
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"gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
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"gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
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"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
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"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
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"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
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"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
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/* FIXME:XX hardcoded. */
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"gfx.ndid": "3",
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"gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
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},
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Children: []DevTreeNode{
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{
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Chip: "cpu_cluster",
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Dev: 0,
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Children: []DevTreeNode{
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{
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Chip: "cpu/intel/socket_rPGA989",
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Children: []DevTreeNode{
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{
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Chip: "lapic",
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Dev: 0,
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},
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},
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},
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{
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Chip: "cpu/intel/model_206ax",
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Comment: "FIXME: check all registers",
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Registers: map[string]string{
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/* FIXME:XX hardcoded. */
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"c1_acpower": "1",
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"c2_acpower": "3",
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"c3_acpower": "5",
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"c1_battery": "1",
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"c2_battery": "3",
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"c3_battery": "5",
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},
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Children: []DevTreeNode{
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{
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Chip: "lapic",
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Dev: 0xacac,
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Disabled: true,
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},
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},
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},
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},
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},
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{
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Chip: "domain",
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Dev: 0,
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PCIController: true,
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ChildPCIBus: 0,
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
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},
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},
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},
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}
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PutPCIDev(addr, "Host bridge")
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/* FIXME:XX some configs are unsupported. */
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KconfigBool[i.variant+"BRIDGE_LVDS"] = true
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KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
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sandybridge ivybridge: Treat native init as first class citizen
This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-09-29 06:39:12 +02:00
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KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true
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2014-10-15 21:51:47 +02:00
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KconfigBool["INTEL_INT15"] = true
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KconfigBool["HAVE_ACPI_TABLES"] = true
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KconfigBool["HAVE_ACPI_RESUME"] = true
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KconfigBool["HAVE_IFD_BIN"] = false
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KconfigBool["HAVE_ME_BIN"] = false
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KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000
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KconfigInt["MAX_CPUS"] = 8
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "cpu/intel/model_206ax/acpi/cpu.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
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2015-08-27 13:31:46 +02:00
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}, DSDTInclude{
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File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
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2014-10-15 21:51:47 +02:00
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})
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}
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func init() {
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RegisterPCI(0x8086, 0x0100, sandybridgemc{variant: "SANDY"})
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RegisterPCI(0x8086, 0x0104, sandybridgemc{variant: "SANDY"})
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RegisterPCI(0x8086, 0x0150, sandybridgemc{variant: "IVY"})
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RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"})
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for _, id := range []uint16{
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0x0102, 0x0106, 0x010a, 0x0112,
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0x0116, 0x0122, 0x0126, 0x0156,
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0x0166,
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} {
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RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
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}
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}
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